High-voltage semiconductor devices with electrostatic discharge (ESD) protection and methods of fabrication are provided. The semiconductor devices include a plurality of transistors on a substrate patterned with one or more common gates extending across a portion of the substrate, and a plurality of first S/D contacts and a plurality of second S/D contacts associated with the common gate(s). The second S/D contacts are disposed over a plurality of carrier-doped regions within the substrate. One or more floating nodes are disposed above the substrate and, at least in part, between second S/D contacts to facilitate defining the plurality of carrier-doped regions within the substrate. For instance, the carrier-doped regions may be defined from a mask with a common carrier-region opening, with the floating node(s) intersecting the common carrier-region opening and facilitating defining, along with the common opening, the plurality of separate carrier-doped regions.

A semiconductor device includes a first transistor and a second transistor. The first transistor includes a first body layer and a first connection part. The second transistor includes a second body layer and a second connection part. A second impedance, which is, in a path between the second connection part and the second body layer, inclusive, a maximum impedance seen by the first source electrode in the second body layer, is greater than a first impedance, which is, in a path between the first connection part and the first body layer, inclusive, a maximum impedance seen by the first source electrode in the first body layer.

A flip-flop circuit includes two inverters and two transmission circuits. The two inverters and the two transmission circuits are implemented using reverse direction high-electron-mobility transistors.

This invention discloses an ESD protection circuit. The ESD protection circuit is arranged on a display panel. It comprises a first conductive via layer electrically connected with a first signal line for outputting signal and a second signal line for inputting signal, and a thin film transistor. A gate of the thin film transistor is electrically connected with a drain, and the second signal line is electrically connected with the gate and/or the drain of the thin film transistor, and the first signal line is electrically connected with a source of the thin film transistor. This invention also discloses a display panel and a display device. In the present invention, the disconnection of the signal line due to electrostatic breakdown is solved.

An electrostatic protection element includes a substrate of a first conductivity type, an epitaxial layer formed on the substrate, the epitaxial layer being of a second conductivity type; a well formed on the epitaxial layer, the well being of the first conductivity type; a transistor formed inside of the well, the transistor including a drain region, a source region formed to face the drain region across a channel region, and a gate formed above the channel region so as to be insulated; and a well contact region of the first conductivity type disposed so as to form an opposing region where the drain region and the well contact region face each other while being separated by a prescribed distance in a direction parallel to at least an extension direction of the gate.

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a first well, a second well, and first and second doped regions. The substrate has heavily doped and lightly doped regions. The lightly doped region is disposed over the heavily doped region. The first well is disposed in the lightly doped region. The first well has a conductive type complementary to a conductive type of the heavily doped and lightly doped regions. The second well is disposed in the substrate over the lightly doped region. A location of the first well overlaps a location of the second well. The first and the second doped regions are located in the second well within the active region, and spaced apart from each other. The first and the second doped regions have a same conductive type complementary to a conductive type of the second well.

A circuit includes a first transistor, a second transistor and a first resistive load. The first transistor has a first terminal coupled to a first reference voltage terminal, a second terminal coupled to a second reference voltage terminal, and a control terminal coupled to the first reference voltage terminal. The second transistor has a first terminal coupled to the second reference voltage terminal, a second terminal coupled to the first reference voltage terminal and the control terminal of the first transistor, and a control terminal coupled to the second reference voltage terminal and the second terminal of the first transistor. The first transistor further comprises a third terminal coupled to the second reference voltage terminal through the first resistive load.

The present application provides a method of preventing thin film transistor (TFT) from electrostatic discharge (ESD) damaging, a method of manufacturing a TFT, and a display panel. By fitting a test data, acquiring relationships between an anti-ESD capability of the TFT and manufacturing parameters of each film layer, according to above-mentioned relationships, disposing the manufacturing parameters of each film layer of the TFT, to prevent the TFT from ESD damaging.

A logic gate includes at least one reverse direction high-electron-mobility transistor. The reverse direction high-electron-mobility transistor includes at least one source connected to a first reference voltage, at least one gate connected to an output, and at least one drain connected to the output. Logic implementing circuitry is connected between the output an additional reference voltage. The logic implementing circuitry includes a first transistor that includes a gate connected to a first input, and a second transistor that includes a gate connected to a second input.

A semiconductor device includes a guard active area formed in a substrate, a plurality of transistors disposed in an element area adjacent to the guard active area, each of the transistors including an active area and a gate structure crossing the active area, and a diode transistor disposed between a first transistor and a second transistor among the transistors, and having a diode gate structure connected to the guard active area, a first active area connected to a gate structure of the first transistor, and a second active area connected to a gate structure of the second transistor.