A circuit includes an output and a reverse direction high-electron-mobility transistor. The reverse direction high-electron-mobility transistor includes a drain connected to the output. The reverse direction high-electron-mobility transistor also includes a source and a gate. A transistor includes a source, a gate connected to a control pin and a drain connected to the gate of the reverse direction high-electron-mobility transistor.

Voltage clamping is provided. A first reverse direction high-electron-mobility transistor includes a source and a gate connected to a voltage clamped line, and a drain connected to a first reference voltage. A second reverse direction high-electron-mobility transistor includes a source and a gate connected to a second reference voltage, and a drain connected to the voltage clamped line.

A logic gate includes at least one reverse direction high-electron-mobility transistor. The reverse direction high-electron-mobility transistor includes at least one source connected to a first reference voltage, at least one gate connected to an output, and at least one drain connected to the output. Logic implementing circuitry is connected between the output an additional reference voltage. The logic implementing circuitry includes a first transistor that includes a gate connected to a first input, and a second transistor that includes a gate connected to a second input.

An electrostatic discharge (ESD) protection device includes a substrate, a first gate group and a second gate group on the substrate, a drain region and a fourth doped region respectively at two sides of the first gate group, a source region and the fourth doped region respectively at two sides of the second gate group, a first doped region in the substrate and surrounded by the drain region, and a second doped region in the substrate and surrounded by the fourth doped region. The drain region and the source region have a first conductivity type. The first doped region and the second doped region have a second conductivity type complementary to the first conductivity type. The drain region is electrically connected to an input/output pad. The source region is electrically connected to a ground pad. The first doped region and the second doped region are electrically connected to each other.

A transistor device includes a substrate a first transistor structure. The first transistor structure includes a first fin structure on the substrate. The first fin structure includes a first doped region, and a second fin structure on the substrate spaced apart from the first fin structure. The second fin structure includes a second doped region and a third doped region spaced apart from the second doped region. The transistor device includes a first electrode on the second fin structure and covering a first end of the second fin structure.

A static electricity prevention circuit of a display device including: a driving circuit configured to drive a display unit that displays an image, at least one clock signal wire configured to transmit a clock signal to the driving circuit, at least one transistor electrically coupled to the clock signal wire, and at least one capacitor including a first electrode coupled to a source electrode and to a drain electrode of the transistor, and a second electrode configured to be maintained at a voltage.

An ESD protection circuit assembly for use in a CMOS manufacturing process is disclosed to include an I/O circuit including a power I/O unit and a signal I/O unit, and an electrostatic discharge clamp circuit connected to the power I/O unit and including a P-type substrate, a series of low voltage P-type structures arranged on the P-type substrate, a plurality of low voltage N-type wells formed on the P-type substrate corresponding to the low voltage P-type structures and a first P-type heavily doped area and a second P-type heavily doped area formed in each low voltage N-type well. By using a series of low voltage P-type structures to provide high ESD tolerance, the ESD protection circuit assembly can be more effectively utilized in the same circuit layout area.

An ESD protection circuit includes at least two unidirectional conduction units arranged between an IO node of an integrated circuit and a positive voltage node, where a first connection node is between the at least two unidirectional conduction units; at least two unidirectional conduction units arranged between the IO node and a negative voltage node, where a second connection node is between the at least two unidirectional conduction units; and a voltage tracking circuit. The input of the voltage tracking circuit is electrically connected to the IO node and the output of the voltage tracking circuit is electrically connected to at least one of the first connection end and the second connection end. By reducing the voltage difference between the IO node and the first connection end or between the IO node and the second connection end, the parasite capacitance associated with the unidirectional conduction unit can be reduced.

A semiconductor apparatus includes a first cell having a first interconnect structure and a second cell having a second interconnect structure. The semiconductor apparatus further includes a first plurality of conductive segments, wherein each conductive segment of the first plurality of conductive segments directly connects a first metal level of the first interconnect structure to a first metal level of the second interconnect structure. The semiconductor apparatus further includes a third cell having a third interconnect structure and a fourth cell having a fourth interconnect structure. The semiconductor apparatus further includes a second plurality of conductive segments, wherein each conductive segment of the second plurality of conductive segments directly connects a second metal level of the third interconnect structure to a second metal level of the fourth interconnect structure, and the second metal level is different from the first metal level.

A semiconductor device includes a first transistor and a second transistor. The first transistor includes a first body layer and a first connection part. The second transistor includes a second body layer and a second connection part. A second impedance, which is, in a path between the second connection part and the second body layer, inclusive, a maximum impedance seen by the first source electrode in the second body layer, is greater than a first impedance, which is, in a path between the first connection part and the first body layer, inclusive, a maximum impedance seen by the first source electrode in the first body layer.