A semiconductor device includes a floating buried doped region, a first doped region disposed between the floating buried doped region and a first major surface, and a semiconductor region disposed between the floating buried doped region and a second major surface. Trench isolation portions extend from the first major surface and terminate within the semiconductor region to define an active region. An insulated trench structure is laterally disposed between the trench isolation portions, terminates within the floating buried doped region, and defines a first portion and a second portion of the active region. A biasing semiconductor device is within the first portion, and a functional semiconductor device is within the second portion. The biasing semiconductor device is adapted to set a potential of the floating buried doped region and adapted to divert parasitic currents away from the functional semiconductor device.

The electrostatic protective device includes an insulator and a semiconductor layer. The semiconductor layer includes a device forming region and a device separating region. The device forming region includes a primary first conductive impurity diffused layer, a body region, a secondary first conductive impurity diffused layer, and a second conductive region that are arranged in order. The second conductive region includes a second conductive impurity diffused layer separated electrically from the body region. The device separating region includes a device separating layer that surrounds the device forming region. A gate electrode is further provided on the body region in the semiconductor layer with an insulating film interposed in between.

A circuit for preventing current backflow includes: a signal connection terminal, a power input terminal, an internal power supply terminal, an electrostatic protection circuit, a first switch element and a cut-off control circuit. The electrostatic protection circuit is coupled to the signal connection terminal and the internal power supply terminal. The first switch element is coupled between the power input terminal and the internal power supply terminal. The cut-off control circuit is coupled to the signal connection terminal, the power input terminal and the first switch element. The cut-off control circuit controls the switching of the first switch element according to a voltage of the signal connection terminal and a voltage of the power input terminal.

An ESD protection circuit assembly for use in a CMOS manufacturing process is disclosed to include an I/O circuit including a power I/O unit and a signal I/O unit, and an electrostatic discharge clamp circuit connected to the power I/O unit and including a P-type substrate, a series of low voltage P-type structures arranged on the P-type substrate, a plurality of low voltage N-type wells formed on the P-type substrate corresponding to the low voltage P-type structures and a first P-type heavily doped area and a second P-type heavily doped area formed in each low voltage N-type well. By using a series of low voltage P-type structures to provide high ESD tolerance, the ESD protection circuit assembly can be more effectively utilized in the same circuit layout area.

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a first well, a second well, and first and second doped regions. The substrate has heavily doped and lightly doped regions. The lightly doped region is disposed over the heavily doped region. The first well is disposed in the lightly doped region. The first well has a conductive type complementary to a conductive type of the heavily doped and lightly doped regions. The second well is disposed in the substrate over the lightly doped region. A location of the first well overlaps a location of the second well. The first and the second doped regions are located in the second well within the active region, and spaced apart from each other. The first and the second doped regions have a same conductive type complementary to a conductive type of the second well.

Methods of forming a high voltage ESD GGNMOS using embedded gradual PN junction in the source region and the resulting devices are provided. Embodiments include a device having a substrate including a device region with an ESD protection circuit; a gate over the device region; a source region in the device region having a N+ implant and a P+ implant laterally separated on a first side of the gate; and a drain region in the device region on a second side of the gate, opposite the first.

Embodiments of an ESD protection device and a method for operating an ESD protection device are described. In one embodiment, an ESD protection device includes a first bipolar device connected to a first node, a second bipolar device connected to the first bipolar device and to a second node, a metal-oxide-semiconductor (MOS) device connected to the first and second nodes and to the first and second bipolar devices and configured to shunt current in response to an ESD pulse received between the first and second nodes, and a diode device connected to the first node, to a third node, to the first and second bipolar devices, and to the MOS device. Other embodiments are also described.

A semiconductor device includes: a first domain including a first high power source line, a first low power source line, and a first power clamp circuit; a second domain including a second high power source line, a second low power source line, and a second power clamp circuit; a third power clamp circuit provided between the second high power source line and the first low power source line; a first relay circuit that receives a signal from the first domain and outputs the signal to the second domain; and a second relay circuit that receives a signal from the second domain and outputs the signal to the first domain, wherein the first relay circuit and the second relay circuit have a circuit portion that is connected to the second high power source line and the first low power source line.

An electronic device for providing ESD protection is formed by a MOS transistor. the MOS transistor includes a source region and a drain region that are separated from each other by a channel-forming region. A first gate is located over the channel forming region. The drain region includes an extension region. A second gate is located over the extension region. The first and second gates are electrically connected to each other.

A semiconductor device includes first to fifth regions, first and second resistive loads. The first region is coupled to a first reference voltage terminal. The first to third regions operate as a first transistor. The fourth region is coupled to a second reference voltage terminal. The fourth to fifth regions operate as a second transistor. The first resistive load couples the second region to the second reference voltage terminal. The second resistive load couples the fifth region to the first reference voltage terminal. The first, third, second, fifth and fourth regions are arranged in order, each of the first, second and third regions corresponds to a first conductive type, and each of the fourth and fifth regions corresponds to a second conductive type.