Embodiments of systems, methods, and apparatus for improving ESD performance and switching time for semiconductor devices including metal-oxide-semiconductor (MOS) field effect transistors (FETs), and particularly to MOSFETs fabricated on Semiconductor-On-Insulator (SOI) and Silicon-On-Sapphire (SOS) substrates.

An integrated circuit device with ESD protection includes a substrate with a well having a first conductivity type formed on the substrate. A drain region has at least one drain diffusion with a second conductivity type implanted in the well and at least one drain conductive insertion on the well. The drain conductive insertion is electrically connected to the drain diffusion and an I/O pad. A source region includes a plurality of source diffusions having the second conductivity type implanted in the well, and the source diffusions are electrically connected to a voltage terminal.

Methods of forming a high voltage ESD GGNMOS using embedded gradual PN junction in the source region and the resulting devices are provided. Embodiments include a device having a substrate including a device region with an ESD protection circuit; a gate over the device region; a source region in the device region having a N+ implant and a P+ implant laterally separated on a first side of the gate; and a drain region in the device region on a second side of the gate, opposite the first.

Provided is a semiconductor device including a gate structure, a first doped region of a first conductivity type, a plurality of second doped regions of a second conductivity type, a third doped region of the first conductivity type, and a plurality of fourth doped regions of the second conductivity type. The gate structure is located on a substrate. The first doped region is located in the substrate on a first side of the gate structure. The second doped regions are located in the first doped region. The second doped regions are separated from each other. The third doped region is located in the substrate on a second side of the gate structure. The fourth doped regions are located in the third doped region. The fourth doped regions are separated from each other. The second doped regions and the fourth doped regions are disposed alternately.

A semiconductor device includes a MOS transistor and an ESD protection element comprised of an NMOS off transistor having a gate potential equal to a ground potential or a well potential. The off transistor has an N-type drain region and a P-type drain region in a drain active region thereof. The P-type region has a potential that is the potential of a P well or a P-type semiconductor substrate. A junction withstand voltage of a PN junction in the drain active region is the withstand voltage of the ESD protection element.

A semiconductor device includes: a first domain including a first high power source line, a first low power source line, and a first power clamp circuit; a second domain including a second high power source line, a second low power source line, and a second power clamp circuit; a third power clamp circuit provided between the second high power source line and the first low power source line; a first relay circuit that receives a signal from the first domain and outputs the signal to the second domain; and a second relay circuit that receives a signal from the second domain and outputs the signal to the first domain, wherein the first relay circuit and the second relay circuit have a circuit portion that is connected to the second high power source line and the first low power source line.

To provide a field-effect transistor and a semiconductor device with improved ESD resistance. A field-effect transistor including: a gate electrode provided on a first-conductivity-type region of a semiconductor substrate with an insulating film provided between the gate electrode and the first-conductivity-type region; a source region of a second conductivity type provided in the semiconductor substrate on one of sides across the gate electrode; a drain region of the second conductivity type provided in the semiconductor substrate on the other of the sides, the other side facing the one side across the gate electrode; a first region of the first conductivity type provided below the drain region and having a higher concentration than the first-conductivity-type region; a second region of the first conductivity type provided to reach a surface in the semiconductor substrate on the other side and having a higher concentration than the first-conductivity-type region; and an extraction electrode connected to the second region.

Electrostatic discharge (ESD) protection structures are provided. A first N-type well region is formed over a P-type semiconductor substrate. First P-type well region and second N-type well region are formed over the first N-type well region. A plurality of first device areas are formed over the first P-type well region. Each first device area includes a plurality of P-type fins extending in a first direction. The P-type fins are divided into a plurality of first groups in each of the first device areas. A second device area is formed over the first P-type well region, and includes a plurality of N-type fins extending in the first direction and surrounded by the first device areas. When an ESD event is present, an ESD current flows sequentially through the P-type fins, the first P-type well region and the N-type fins.

A pixel substrate includes a photoelectric conversion element. The photoelectric conversion element includes a doped region and a substrate region. The doped region and the substrate region form a pn junction. A pixel circuit is electrically connected to a first supply line and the photoelectric conversion element. A protection circuit is configured to short-circuit the first supply line and the substrate region when a voltage difference between the first supply line and the substrate region falls below a negative threshold voltage.

A semiconductor device according to an embodiment includes a semiconductor substrate having a first plane and a second plane, a plurality of first semiconductor areas provided on the first plane, a plurality of second semiconductor areas provided between the plurality of first semiconductor areas, a plurality of insulator regions provided between the first semiconductor areas and the second semiconductor areas, first-conductivity-type drain regions provided in the first semiconductor areas, first-conductivity-type source regions provided in the second semiconductor areas, gate electrodes, first-conductivity-type first impurity regions that are provided between the first-conductivity-type drain regions and the second plane and have a lower first-conductivity-type impurity concentration than the first-conductivity-type drain regions, and a plurality of second-conductivity-type second impurity regions provided between the first-conductivity-type source regions and the second plane. The width of at least one of the plurality of first semiconductor areas is greater than the width of the other first semiconductor areas.