An IC device includes a first power terminal, an IO pad, a first ESD protection device coupled between the first power terminal and IO pad, a first trigger current source device coupled between the first power terminal and IO pad, and a semiconductor substrate over which the first ESD protection device and first trigger current source device are formed. The first ESD protection device includes a parasitic BJT having a collector and an emitter coupled between the IO pad and first power terminal, and a base coupled via a substrate resistance to a well tap coupled to the first power terminal. The first trigger current source device, in response to an ESD voltage on the IO pad, becomes conductive and causes discharge of the ESD voltage through the first ESD protection device to the first power terminal.

A drain extended metal oxide semiconductor (MOS) includes a substrate having a semiconductor. A gate is located on the semiconductor, a source is located on the semiconductor and on one side of the gate, and a drain is located on the semiconductor and on another side of said gate. The MOS includes least one first finger having a first finger drain component located adjacent the drain, the first finger drain component has a silicide layer. At least one second finger has a second finger drain component located adjacent the drain, the second finger drain component has less silicide than the first finger drain component.

An integrated artificial neuron device includes an input signal node, an output signal node and a reference supply node. An integrator circuit receives and integrates an input signal to produce an integrated signal. A generator circuit receives the integrated signal and, when the integrated signal exceeds a threshold, delivers the output signal. The integrator circuit includes a main capacitor coupled between the input signal node and the reference supply node. The generator circuit includes a main MOS transistor coupled between the input signal node and the output signal node. The main MOS transistor has a gate that is coupled to the output signal node, and a substrate that is mutually coupled to the gate.

A semiconductor device includes an off transistor using an NMOS as an ESD protection element that has N-type drain region (102), and P-type drain region (103) in a drain active region (105) . The P-type drain region (103) has a potential same as a potential of a P well or a P-type semiconductor substrate (106), and the ESD protection element has a withstand voltage that is a junction withstand voltage of a PN junction in the drain active region (105) .

A bipolar junction transistor is configured to provide electrostatic discharge (ESD) protection for an integrated circuit. The bipolar junction transistor includes a substrate configured to function as a gate for the bipolar junction transistor. At least one drain finger extends in a first direction on a first surface of the substrate and is configured to function as a collector for the bipolar junction transistor. At least one source finger extends in the first direction on the first surface of the substrate and is configured to function as an emitter for the bipolar junction transistor. The at least one source finger includes a pickup region that is configured to set a substrate potential.

Embodiments herein may describe techniques for an integrated circuit including a MOSFET having a source area, a channel area, a gate electrode, and a drain area. The channel area may include a first channel region with a dopant of a first concentration next to the source area, and a second channel region with the dopant of a second concentration higher than the first concentration next to the drain area. A source electrode may be in contact with the source area, a gate oxide layer above the channel area, and the gate electrode above the gate oxide layer. A first resistance exists between the source electrode and the gate electrode. A second resistance exists between the source electrode, the gate electrode, and a path through the gate oxide layer to couple the source electrode and the gate electrode after a programming operation is performed. Other embodiments may be described and/or claimed.

A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a first well region that has first conductive type therein. The semiconductor device structure also includes a first doped region embedded in the first well region, and having a second conductive type that is different from the first conductive type. The semiconductor device structure further includes a second well region that has the second conductive type. In addition, the semiconductor device structure includes a first metal electrode disposed on the first doped region of the semiconductor substrate and a second metal electrode disposed on the second well region of the semiconductor substrate.

A semiconductor device includes: a first domain including a first high power source line, a first low power source line, and a first power clamp circuit; a second domain including a second high power source line, a second low power source line, and a second power clamp circuit; a third power clamp circuit provided between the second high power source line and the first low power source line; a first relay circuit that receives a signal from the first domain and outputs the signal to the second domain; and a second relay circuit that receives a signal from the second domain and outputs the signal to the first domain, wherein the first relay circuit and the second relay circuit have a circuit portion that is connected to the second high power source line and the first low power source line.

A modeling circuit of a field effect transistor includes a first field effect transistor, a first bipolar transistor, a second bipolar transistor and a substrate resistor. The first bipolar transistor has a collector electrode connected to a first node corresponding to a first electrode of the first field effect transistor, an emitter electrode connected to a second node corresponding to a second electrode of the first field effect transistor, and a base electrode. The second bipolar transistor has a collector electrode connected to the second node, an emitter electrode connected to the first node, and a base electrode connected to the base electrode of the first bipolar transistor. The substrate resistor is connected between the base electrodes of the first and second bipolar transistors and a first surface of a semiconductor substrate on which the first field effect transistor is formed.

A semiconductor chip may have at least one p-channel field effect transistor (FET), at least one n-channel FET, a first and a second power supply terminal, wherein the at least one n-channel FET, if supplied with the upper supply potential at its gate, supplies the lower supply potential to the gate of the at least one p-channel FET and the at least one p-channel FET, if supplied with the lower supply potential at its gate, supplies the upper supply potential to the gate of the at least one n-channel FET, a precharge circuit to precharge the circuit to a first state, and a detection circuit configured to output an alarm signal if the circuit enters a second state.