A MOSFET fabricated in a semiconductor substrate, includes: a gate oxide region formed atop the semiconductor substrate; a gate polysilicon region formed on the gate oxide region; a source region of a first doping type formed in the semiconductor substrate and located at a first side of the gate polysilicon region; and a drain region of the first doping type formed in the semiconductor substrate and located at a second side of the gate polysilicon region. The gate polysilicon region has a first sub-region of the first doping type, a second sub-region of the first doping type, and a third sub-region of a second doping type, wherein the first sub-region is laterally adjacent to the source region, the second sub-region is laterally adjacent to the drain region, and the third sub-region is formed laterally between the first and second sub-regions.

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a first well, a second well and doped regions. The substrate has heavily doped and lightly doped regions over the heavily doped region. The first wells are disposed in the lightly doped region and arranged as an array. The first wells have a conductive type opposite to a conductive type of the heavily doped and lightly doped regions. The second well is disposed in the substrate over the lightly doped region, and has an active region defined by an isolation structure. The first wells are overlapped with the second well. Top ends of the first wells are lower than a bottom end of the second well. The doped regions are separately located in the active region, and have a conductive type opposite to a conductive type of the second well.

Voltage clamping and level shifting is provided. A first reverse direction high-electron-mobility transistor includes a source connected to an input pad, and a drain connected to a first reference voltage. A second reverse direction high-electron-mobility transistor includes a source and a gate connected to a second reference voltage, and a drain connected to the input pad. A gate of the first reverse direction high-electron-mobility transistor is connected to the second reference voltage. Level shifting is provided by an arrangement of three high-electron-mobility transistor and a resistive element

An electrostatic discharge protection structure includes a laterally diffused metal oxide semiconductor (LDMOS) device. The LDMOS device includes an embedded bipolar junction transistor. A gate, a source, a buried layer lead-out area, and a substrate lead-out area of the LDMOS device are grounded. A drain and a body region lead-out area of the LDMOS device are electrically connected to a pad input/output terminal. In an embodiment, the embedded bipolar junction transistor includes a PNP transistor operative to transmit a reverse electrostatic discharge current. An N+ drain, a gate, an N+ source, and a P+ substrate lead-out area form a grounded-gate NMOS (GGNMOS) operative to transmit a forward electrostatic discharge current.

A semiconductor device includes a first well, a first region and fourth regions of a first conductivity type as well as second regions, a third region, a second well of the second conductivity type. A first region is disposed in the first well and coupled to a first reference voltage terminal. Second regions are disposed in the first well, wherein one of the second regions is coupled to the first reference voltage terminal, and the second regions and the first well are included in a first transistor. A third region is disposed in the first well. A first resistive load is coupled between the third region and a second reference voltage terminal. A second well is coupled to the first well. Fourth regions are disposed in the second well, wherein the second well and at least one of the fourth regions are included in a second transistor.

A display device includes a substrate including a display area and a non-display area adjacent to the display area, a plurality of pixels being located in the display area, a driver located in the non-display area, a data line electrically connected to the driver to transmit a data signal to each of the plurality of pixels, a first driving voltage line and a second driving voltage line in the non-display area, and an antistatic portion in the non-display area and connected between the data line and the first driving voltage line. The display area further includes at least one first area electrically connected to one side of the driver and at least one second area electrically connected to another side of the driver. In addition, the non-display area includes a first non-display area corresponding to the first area and a second non-display area corresponding to the second area.

An electro-static discharge (ESD) protection circuit is electrically connected to a first pad and a second pad. The ESD protection circuit includes an ESD transistor having a control terminal, a first terminal electrically connected to the first pad, a second terminal electrically connected to the second pad, and a substrate end; and an electro-static pulse detection circuit having an upper terminal electrically connected to the first pad, a lower terminal electrically connected to the second pad, and an output terminal electrically connected to the control terminal and the substrate end of the ESD transistor.

This application provides an electrostatic discharge protection circuit, disposed between a first pad and a second pad of a circuit. The electrostatic discharge protection circuit includes: a main discharge transistor and an auxiliary discharge transistor, both configured to be conductive after an electrostatic pulse caused by electrostatic charges is detected on the first pad to discharge the electrostatic charges to the second pad. Conduction time of the main discharge transistor is prior to conduction time of the auxiliary discharge transistor. An amount of the electrostatic charges discharged by the main discharge transistor is greater than an amount of the electrostatic charges discharged by the auxiliary discharge transistor. The circuit provided in this application can prolong bleeding of the electrostatic charges time and has a sufficient electrostatic discharge capability.

A semiconductor device includes a P-doped well having a first concentration of P-type dopants in the substrate; a P-doped region having a second concentration of P-type dopants in the substrate and extending around a perimeter of the P-doped well; a shallow trench isolation structure (STI) between the P-doped well and the P-doped region; an active area on the substrate, the active area including an emitter region and a collector region; a deep trench isolation structure (DTI) extending through the active area and between the emitter region and the collector region; and an electrical connection between the emitter region and the P-doped region.

An avalanche-protected field effect transistor includes, within a semiconductor substrate, a body semiconductor layer and a doped body contact region having a doping of a first conductivity type, and a source region a drain region having a doping of a second conductivity type. A buried first-conductivity-type well may be located within the semiconductor substrate. The buried first-conductivity-type well underlies, and has an areal overlap in a plan view with, the drain region, and is vertically spaced apart from the drain region, and has a higher atomic concentration of dopants of the first conductivity type than the body semiconductor layer. The configuration of the field effect transistor induces more than 90% of impact ionization electrical charges during avalanche breakdown to flow from the source region, to pass through the buried first-conductivity-type well, and to impinge on a bottom surface of the drain region.