A semiconductor device for protecting an internal circuit includes a transistor, a first doping region, and a second doping region. The transistor includes a gate terminal, a source terminal, and a drain terminal. The gate terminal is coupled to a ground. The source terminal is coupled to the internal circuit. The drain terminal is coupled to an input/output pad. The first doping region has a first conductive type. The second doping region has a second conductive type and is adjacent to the first doping region. The first doping region and the second doping region form the gate terminal. The first conductive type is different from the second conductive type.

An electrostatic discharge unit, an array substrate and a display panel are provided. The electrostatic discharge unit includes: an active layer; a first gate electrode and a second gate electrode which are spaced apart from each other and are insulated from the active layer; and a first electrode and a second electrode which are spaced apart from each other and are respectively connected to the active layer. The first gate electrode is electrically connected to the first electrode, and the second gate electrode is electrically connected to the second electrode.

A semiconductor device includes first well regions in a substrate and spaced apart from each other, a connection doped region between the first well regions, and a first interconnection line electrically connected to the connection doped region through a first contact. The first well regions and the connection doped region include impurities of a first conductivity type, and a concentration of the impurities in the connection doped region is higher than that in the first well regions. The first well regions extend into the substrate to a depth larger than that of the connection doped region. A first portion of the connection doped region is disposed in the first well regions and a second portion of the connection doped region contacts the substrate.

A sensor substrate includes a base substrate, a black matrix pattern, a sensing electrode pattern, a driving electrode pattern, and at least one bridge line. The black matrix pattern is disposed on the base substrate and divides the base substrate into a light transmission area and a light blocking area. The sensing electrode pattern includes a plurality of first unit patterns arranged in association with a first direction. The driving electrode pattern includes a plurality of second unit patterns arranged in association with a second direction and disposed adjacent to the plurality of first unit patterns. The at least one bridge line is connected between at least two of the plurality of first unit patterns or between at least two of the plurality of second unit patterns.

An electrostatic discharge (ESD) protection structure that provides snapback protections to one or more high voltage circuit components. The ESD protection structure can be integrated along a peripheral region of a high voltage circuit, such as a high side gate driver of a driver circuit. The ESD protection structure includes a p-channel device and an n-channel device. The p-channel device includes an n-type barrier region circumscribing a p-type drain region with an n-type body region. The p-channel device may be positioned adjacent to the n-channel device and a high voltage junction diode.

To perform protection from damage in a semiconductor device manufacturing process while suppressing an increase in an area. A protection circuit includes at least one protection transistor. A first diffusion layer of the protection transistor is connected to a terminal of a protected circuit. A second diffusion layer of the protection transistor is connected to a ground level. A gate and a well of the protection transistor are connected to power supply lines. When receiving plasma induced damage, voltages of the second diffusion layer, the gate, and the well of the protection transistor are relatively lowered, and the protection transistor operates in a forward bias mode.

In a particular implementation, an apparatus to control clamping devices includes a first control circuit and a second control circuit. The first control circuit is responsive to a detection signal and generates a first drive signal to control a body diode of a clamping device. The second control circuit is responsive to the detection signal and generates a second drive signal to control the gate terminal of the clamping device.

The application relates to a device and method for measuring a high electron mobility transistor. The device provided includes a controller, a protection circuit, a load circuit and a switching circuit electrically connected between the load circuit and the protection circuit. The controller is configured to provide a first control signal having a first value to a semiconductor component at a first time point and provide a second control signal having a second value to the switching circuit at a second time point. The semiconductor component is turned on by the first value of the first control signal, and the switching circuit is turned on by the second value of the second control signal. The second time point is later than the first time point.

A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a first well region that has first conductive type therein. The semiconductor device structure also includes a first doped region embedded in the first well region, and having a second conductive type that is different from the first conductive type. The semiconductor device structure further includes a second well region that has the second conductive type. In addition, the semiconductor device structure includes a first metal electrode disposed on the first doped region of the semiconductor substrate and a second metal electrode disposed on the second well region of the semiconductor substrate.

An electrostatic discharge (ESD) protection device and a method thereof are presented. A well is disposed in a substrate. A gate is disposed on the well. A source region and a drain region are located in the well and at two opposite sides of the gate respectively. A first doped region is located in the drain region, wherein the first doped region is electrically connected to the drain region. A second doped region is located in the source region, wherein the second doped region is electrically connected to the source region. A third doped region is located in the well and at a side of the drain region opposite to the gate. A fourth doped region is located in the well and at a side of the source region opposite to the gate, wherein the fourth doped region is electrically connected to the third doped region.