The present disclosure provides a power clamp circuit, a chip, and a dual-clamp method. The power clamp circuit is applied to a circuit system to monitor the power supply voltage of the circuit system and includes: an EOS protection module, for outputting an EOS protection triggering signal when it is determined that the circuit system is electrically overstressed based on the power supply voltage; an ESD protection module, for outputting an ESD protection triggering signal when it is determined that an electrostatic event is present in the circuit system based on the power supply voltage; a switch control module, for turning on a discharge path based on the EOS protection signal to discharge an EOS current, and turning on the discharge path based on the ESD protection signal to discharge an electrostatic current.

Semiconductor device structures with substrate biasing, methods of forming a semiconductor device structure with substrate biasing, and methods of operating a semiconductor device structure with substrate biasing. A substrate contact is coupled to a portion of a bulk semiconductor substrate in a device region. The substrate contact is configured to be biased with a negative bias voltage. A field-effect transistor includes a semiconductor body in the device region of the bulk semiconductor substrate. The semiconductor body is electrically isolated from the portion of the bulk semiconductor substrate.

A trigger circuit includes a first capacitor and a second capacitor connected in series, a control device and an output of the trigger circuit. The first capacitor is connected to a first voltage rail and to a common node. The second capacitor is connected to a second voltage rail and to the common node. The control device has a first terminal that is coupled to the common node and a control terminal to receive a control signal. The control signal may be decoupled from transients on the first voltage rail and the second voltage rail. The output of the trigger circuit is coupled to the common node.

An electrostatic discharge protection circuit, including a discharge switch, a first transistor, an inverter, and a feedback circuit, is provided. The discharge switch is coupled between a first power rail and a second power rail, and may be turned on or cut off according to a control voltage. The first transistor has a first end coupled to the first power rail. A control end of the first transistor receives the control voltage. The inverter is coupled between a second end of the first transistor and a control end of the discharge switch. The feedback circuit is coupled between an output end and an input end of the inverter and is configured to determine whether to provide a turn-on path between the input end of the inverter and the second power rail according to the control voltage.

A surge protection circuit includes a DC trigger circuit that generates a trigger signal when a surge pulse occurs, and a current conducting unit, coupled to the DC trigger circuit, that generates a first clamp voltage as an output voltage of the surge protection circuit and conducts surge currents to ground in response to the trigger signal. The DC trigger circuit includes a surge detection circuit and a first amplification circuit. The surge detection circuit detects if a surge pulse occurs, and triggers the first amplification circuit to generate the trigger signal when the surge detection circuit detects a surge pulse.

A transient voltage protection circuit includes a first input/output pad, a second input/output pad, and a trigger circuit coupled between the first input/output pad and the second input/output pad. The trigger circuit includes a first trigger element which includes a first input/output node, a second input/output node, a third input/output node, and a first substrate diode coupled to the third input/output node of the first trigger element. The trigger circuit further includes a first resistor coupled between the first input/output node of the first trigger element and the second input/output node of the first trigger element. The trigger circuit further includes a second trigger element which includes a first input/output node, a second input/output node, a third input/output node, wherein the second input/output node of the first trigger element is coupled to the first input/output node of the second trigger element, and a second substrate diode coupled to the third input/output node of the second trigger element. The trigger circuit further includes a second resistor coupled between the first input/output node of the second trigger element and the second input/output node of the second trigger element.

A protection circuit includes a first PMOS and a first PDMOS receiving input of voltage of a voltage dividing point of voltage input from an external power supply terminal, and a second PMOS and a second PDMOS receiving input of drain output voltage of the first PDMOS. The first PMOS is connected on the external power supply terminal side of the first PDMOS, and the second PMOS is connected on the external power supply terminal side of the second PDMOS. During overvoltage application, the voltage of the voltage dividing point is clamped to the breakdown voltage of a Zener diode, the second PDMOS turns OFF, and supply to an integrated circuit protected from overvoltage is cut off. When the voltage source is connected in reverse, parasitic diodes of the first and second PMOSs are reverse-biased and the flow of current in a path through the parasitic diodes is inhibited.

A semiconductor device includes a substrate having a semiconductor surface doped a second dopant type with a buried layer (BL) doped a first dopant type. First, second and third well regions doped the second dopant type are on top of the BL. Second doped regions doped the first dopant type on top of and contacting the BL arraigned as a first well ring and second well ring are around the first and third well regions respectively. At least one high-injection component including the first well region is surrounded by the first well ring. At least one component including the third well region is surrounded by the second well ring. An npn or pnp guard wall pocket including a wall of the first and second well rings, and the second well region is between the high-injection component and the component.

A chip includes a first die, a second die, a first and a second through-silicon vias, a first protection circuit, and a second protection circuit. The first die has a first operational voltage node and a first reference voltage node. The second die has a second operational voltage node and a second reference voltage node. The first and the second through-silicon vias are configured to couple the first die and the second die. The first protection circuit is coupled between the first operational voltage node and the first through-silicon via. The second protection circuit is coupled between the first reference voltage node and the second through-silicon via. The first through-silicon via is further coupled to the second reference voltage node or the second operational voltage node. The second through-silicon via is further coupled to the first reference voltage node or the first operational voltage node.

An electrostatic discharge (ESD) protection circuit is coupled between first and second power supply buses. The ESD protection circuit includes a detection circuit; a pull-up circuit, coupled to the detection circuit, comprising at least a first n-type transistor; a pull-down circuit, coupled to the pull-up circuit, comprising at least a second n-type transistor; and a bypass circuit, coupled to the pull-up and pull-down circuits, wherein the detection circuit is configured to detect whether an ESD event is present on either the first or the second bus so as to cause the pull-up and pull-down circuits to selectively enable the bypass circuit for providing a discharging path between the first and second power supply buses.