An electrostatic discharge (ESD) protection circuit has an ESD detection circuit, an ESD clamp circuit, and a leakage current reduction circuit. The ESD detection circuit generates an ESD trigger signal when an ESD event is detected in a normal mode. The ESD clamp circuit has a first transistor and a second transistor. The first transistor has a first connection terminal coupled to a first power rail, a control terminal, and a second connection terminal. A bias voltage is supplied to the control terminal of the first transistor in the normal mode. The second transistor has a first connection terminal coupled to the second connection terminal of the first transistor, a control terminal, and a second connection terminal coupled to a second power rail. The ESD trigger signal is transmitted to the control terminal of the second transistor. The leakage current reduction circuit provides the bias voltage to the first transistor.

To prevent damage on an element even when a voltage high enough to break the element is input. A semiconductor device of the invention operates with a first voltage and includes a protection circuit which changes the value of the first voltage when the absolute value of the first voltage is higher than a reference value. The protection circuit includes: a control signal generation circuit generating a second voltage based on the first voltage and outputting the generated second voltage; and a voltage control circuit. The voltage control circuit includes a transistor which has a source, a drain, and a gate, and which is turned on or off depending on the second voltage input to the gate and thus controls whether the value of the first voltage is changed based on the amount of current flowing between the source and the drain. The transistor also includes an oxide semiconductor layer.

An integrated artificial neuron device includes an input signal node, an output signal node and a reference supply node. An integrator circuit receives and integrates an input signal to produce an integrated signal. A generator circuit receives the integrated signal and, when the integrated signal exceeds a threshold, delivers the output signal. The integrator circuit includes a main capacitor coupled between the input signal node and the reference supply node. The generator circuit includes a main MOS transistor coupled between the input signal node and the output signal node. The main MOS transistor has a gate that is coupled to the output signal node, and a substrate that is mutually coupled to the gate.

This disclosure provides an ESD protection circuit coupled to a first and a second terminals of a differential-pair circuit. The ESD protection circuit includes: an ESD sensing unit coupled to the first and the second terminals and sensing electrical changes at the first and the second terminals to generate a first trigger signal; and a first discharging unit coupled to the ESD sensing unit and turning on a first discharging path according to the first trigger signal.

A switch includes an input terminal and an output terminal. The switch also includes a first stack having transistors coupled in series, and a second stack having transistors coupled in series. The first stack and the second stack are connected in parallel with one another.

An electrostatic discharge (ESD) protection device including an ESD protection unit and a control circuit is provided. When a voltage level of a signal received by a signal input terminal reaches an ESD protection level, the ESD protection unit transmits the signal from the signal input terminal to the system voltage terminal. The control circuit controls a conduction state between the signal input terminal and the system voltage terminal through the ESD protection unit. The control circuit generates a control voltage according to the voltage level of the signal received by the signal input terminal and a system voltage level of the system voltage terminal to control the ESD protection unit, and to prevent the ESD protection unit from transmitting the signal to the system voltage terminal when the voltage level of the signal received by the signal input terminal does not reach the ESD protection level.

Described is an apparatus which comprises: a pad; a first transistor coupled in series with a second transistor and coupled to the pad; and a self-biasing circuit to bias the first transistor such that the first transistor is to be weakly biased during an electrostatic discharge (ESD) event. Described is also an apparatus which comprises: a first transistor; and a first local ballast resistor formed of a trench contact (TCN) layer, the first local ballast resistor having a first terminal coupled to either the drain or source terminal of the first transistor.

A switching circuit disclosed, herein, includes a main MOSFET 12, a control MOSFET 14, and a diode 16. The main MOSFET is formed in a SiC semiconductor layer. A channel type of the main MOSFET is a first conductivity type. A channel type of the control MOSFET is a second conductivity type. A source of the control MOSFET is connected to-a gate of the main MOS-FET. A cathode of the diode is connected to a gate of one of the main MOSFET and the control MOSFET. An anode of the diode is connected to a gate of the other of the main MOSFET and the control MOSFET. A channel type of the one is an n-type. A channel type of the other is a p-type.

Apparatus and methods for transient overstress protection with false condition shutdown are provided herein. In certain configurations, a high-voltage tolerant actively-controlled protection circuit includes a transient overstress detection circuit, a clamp circuit electrically connected between a first node and a second node, a bias circuit that biases the clamp circuit, and a false condition shutdown circuit. The transient overstress detection circuit generates a detection signal indicating whether or not a transient overstress event is detected between the first and second nodes. Additionally, the false condition shutdown circuit generates a false condition shutdown signal based on low pass filtering a voltage difference between the first and second nodes, thereby determining independently whether or not power is present. The bias circuit controls operation of the clamp circuit in an on state or an off state based on the detection signal and the false condition shutdown signal.

An electrostatic discharge circuit may include a control voltage generation circuit, an electrostatic detection circuit, a driving control circuit and a discharge driving circuit. The control voltage generation circuit may generate first to third control voltages through a division operation on a supply voltage. The electrostatic detection circuit may set a first setup voltage based on the first control voltage, and detect static electricity transferred through the first setup voltage. The driving control circuit may set a second setup voltage based on the second control voltage, and generate a driving control signal. The discharge driving circuit may set a third setup voltage based on the third control voltage, and perform a discharge operation on static electricity.