An electrostatic discharge (ESD) protection circuit includes an ESD detector connected between a pad and a first power source and configured to generate a detection signal when ESD is detected at the pad, a switch transistor including a gate controlled by the detection signal and a source and a drain connected between the pad and the memory, and a leakage current prevention circuit including a first transistor including a first gate connected to a second power source and a source and a drain connected between the pad and a first node, and a second transistor including a second gate connected to the pad and a source and a drain connected between the first node and the second power source. The first node is connected to or in electrical communication with a bulk node of the switch transistor.

The present disclosure provides an electrostatic protection circuit and an electronic device. The electrostatic protection circuit is connected to a first end point and a second end point of a power device. The electrostatic protection circuit is configured to allow bilateral electrostatic protection between the first end point and the second end point of the power device. The power device includes a transverse high-electron-mobility transistor (HEMT).

The present disclosure provides a display panel static electricity protection device (400), static electricity protection method, and a display device (100), including a detection sub-circuit (401), a detection sub-circuit (401), a discharge circuit (402) connected with the driving chip (301), a current driving sub-circuit (403) connected with the detection sub-circuit (401), the discharge circuit (402), and a discharge terminal (404), and the discharge terminal (404) connected with a grounding wire of the driving circuit board. The detection sub-circuit (401) detects static electricity, the current driving sub-circuit (403) inputs and detects current in the detection sub-circuit (401) to open or close the discharge circuit (402). The static electricity is discharged to the discharge terminal (404) through the discharge circuit (402) and the current driving sub-circuit (403).

A semiconductor device arrangement and a method of operating a semiconductor device arrangement. The semiconductor device can be arranged for bidirectional operation. The semiconductor device arrangement can comprise: a field effect transistor comprising first and second input terminals; a control terminal; a first diode connected between the first terminal and the control terminal; and a second diode connected between the second terminal and the control terminal; wherein the first terminal and the second terminal are configured and arranged to be connected to respective signal lines.

A surge protection device for providing bidirectional detections of one or more surge events. The device has low dynamic resistance during a surge protection mode, and it conducts ultra-low leakage current outside of the surge protection mode. In one implementation, the device includes first and second power transistors, a sensing circuit, and a driver circuit. The first power transistor includes a first source terminal that is coupled to the substrate, and the second power transistor includes a second source terminal that is coupled to the substrate. The sensing circuit is configured to detect a voltage of the first pin relative to the second pin and generate a sense signal when the voltage exceeds a threshold. The driver circuit is configured to generate a driver signal based on the sense signal and output the driver signal to at least one of the first or second gate terminal.

The present application relates to electrostatic protection circuit, integrated circuit and electrostatic discharge method. The electrostatic protection circuit includes: pulse detection unit configured to detect an electrostatic pulse, with first terminal connected to first pad, second terminal connected to second pad, and output terminal outputting a detection result signal; discharge transistor with gate connected to the pulse detection unit, drain connected to the first pad, and source connected to the second pad, configured to conduct the source and the drain when static electricity occurs in the first pad or the second pad, to discharge electrostatic charges; and processing unit connected to the pulse detection unit and the discharge transistor, configured to control ON and OFF of the discharge transistor based on the detection result signal, the processing unit including: a feedback delay circuit configured to extend an ON period of the discharge transistor during the discharge of the electrostatic charges.

An electrostatic discharge (ESD) circuit includes: a cascade of NMOS transistors including a first NMOS transistor operatively cascaded to a second NMOS transistor wherein the cascade of NMOS transistors is operatively coupled to a first bus that receives an ESD pulse signal; a first single-gate-oxide ESD control circuit coupled to the first NMOS transistor and configured to turn on the first NMOS transistor during an ESD event, the first single-gate-oxide control circuit coupled between the first bus at a first voltage and a first node at a second voltage, wherein the first voltage is higher than the second voltage; a second single-gate-oxide control circuit operatively coupled to the second NMOS transistor and configured to turn on the second NMOS transistor during an ESD event and to turn off the second NMOS transistor during a normal operation, wherein the second single-gate-oxide control circuit is coupled between the first node at the second voltage and a second bus at a ground voltage, wherein the second voltage is higher than the ground voltage; and a voltage divider circuit operatively coupled to the first bus at the first voltage and the second bus at the ground voltage, wherein the voltage divider circuit is operatively coupled to the first single-gate-oxide ESD control circuit and the second single-gate-oxide ESD control circuit at the first node.

Semiconductor device structures with substrate biasing, methods of forming a semiconductor device structure with substrate biasing, and methods of operating a semiconductor device structure with substrate biasing. A substrate contact is coupled to a portion of a bulk semiconductor substrate in a device region. The substrate contact is configured to be biased with a negative bias voltage. A field-effect transistor includes a semiconductor body in the device region of the bulk semiconductor substrate. The semiconductor body is electrically isolated from the portion of the bulk semiconductor substrate.

Systems and methods for protecting a device from an electrostatic discharge (ESD) event are provided. A resistor-capacitor (RC) trigger circuit and a driver circuit are provided. The RC trigger circuit is configured to provide an ESD protection signal to the driver circuit. A discharge circuit includes a first metal oxide semiconductor (MOS) transistor and a second MOS transistor connected in series between a first voltage potential and a second voltage potential. The driver circuit provides one or more signals for turning the first and second MOS transistors on and off.

A device is disclosed herein. The device includes an electrostatic discharge (ESD) detector, a bias generator, and an ESD driver including at least two transistors coupled to each other in series. The ESD detector is configured to detect an input signal and generate a detection signal in response to an ESD event being detected. The bias generator is configured to generate a bias signal according to the detection signal. The at least two transistors are controlled according to the bias signal and a logic control signal, and the input signal is applied across the at least two transistors.