Methods and apparatuses for protecting a low voltage (LV) circuit implemented with LV transistors are presented. Protection is provided via a protection circuit operating in a high voltage domain defined by a varying supply voltage and a reference ground. The protection circuit generates high side, V.sub.H, and low side, V.sub.L, voltages to the LV circuit, while protecting the LV circuits from high voltage and maintaining a minimum difference voltage, V.sub.H−V.sub.L. The protection circuit generates the difference voltage based on a voltage across a resistor of a resistor ladder that is coupled between the varying supply voltage and the reference ground. The protection circuit includes a clamp circuit that limits the minimum difference voltage for low values of the supply voltage. The protection circuit generates the difference voltage according to a nonlinear transfer function of the supply voltage that includes two linear segments having different slopes and a nonlinear segment that provides a continuous and smooth transition between the two linear segments.

An electrostatic discharge (ESD) protection circuit includes a first transistor, a second transistor, a capacitor, a voltage dividing circuit, and a first diode. The first transistor is coupled between a first power rail and a second power rail. The second transistor is coupled between the first power rail and the second power rail. A bulk of the second transistor is coupled to a control terminal of the first transistor. The capacitor is coupled between the first power rail and a control terminal of the second transistor. The voltage dividing circuit is coupled between the control terminal of the second transistor and the second power rail, and has a divided voltage output terminal coupled to the bulk of the second transistor. The first diode is coupled between the divided voltage output terminal and the second power rail.

A voltage tracking circuit includes first, second, third and fourth transistors. The first transistor is in a first well, and includes a first gate, a first drain and a first source coupled to a first voltage supply. The second transistor includes a second gate, a second drain and a second source. The second source is coupled to the first drain. The second gate is coupled to the first gate and a pad voltage terminal. The second body terminal is coupled to a first node. The third transistor includes a third gate, a third drain and a third source. The fourth transistor includes a fourth gate, a fourth drain and a fourth source. The fourth drain is coupled to the third source. The fourth source is coupled to the pad voltage terminal. The second transistor is in a second well different from the first well, and is separated from the first well in a first direction.

An electrostatic discharge (ESD) protection circuit includes a plurality of transistors each including a gate terminal, a drain terminal, and a source terminal, a first connection line connected to the drain terminals of the plurality of transistors, a second connection line connected to the source terminals of the plurality of transistors, a third connection line connected to the gate terminals of the plurality of transistors, an external resistor connected to the third connection line, and a ground terminal connected to the external resistor. The external resistor includes a first resistor and a second resistor connected to each other in parallel.

A simultaneous dual-band image sensor having a plurality of pixels includes a substrate, a common ground on the substrate, wherein each pixel includes a Band 1 absorber layer on the common ground layer, a barrier layer on the Band 1 absorber layer, a Band 2 absorber layer on the barrier layer, a ring opening in the pixel formed by a removed portion of the Band 2 absorber layer, a removed portion of the barrier layer and a removed portion of the Band 1 absorber layer, wherein the ring opening does not extend through the Band 1 absorber layer, a first contact on a portion of the Band 2 absorber layer inside the ring, and a second contact on a portion of the Band 2 absorber layer outside the ring. The Band 1 absorber layer and the Band 2 absorber layer are n-type, or the Band 1 absorber layer and the Band 2 absorber layer are p-type.

An electrostatic discharge protection circuit includes an electrostatic discharge clamp between a first rail and a second rail, a trigger device configured to activate the electrostatic discharge clamp in response to an electrostatic discharge event, and a charge dissipation element between the first rail and the second rail to dissipate a residual charge at an input of the trigger device.

A semiconductor device includes: an ESD protection circuit including a first n-channel MOS transistor provided between a signal terminal and a ground wire; and a control circuit electrically connected to the signal terminal, wherein, while a signal of a high level is being supplied to the signal terminal, the control circuit outputs a first voltage dropped from a high-level voltage of the signal to a gate of the first n-channel MOS transistor, and in response to a surge due to ESD being input into the signal terminal, outputs a second voltage lower than the first voltage to the gate of the first n-channel MOS transistor.

An artificial-neuron device includes an integration-generation circuit coupled between an input at which an input signal is received and an output at which an output signal is delivered, and a refractory circuit inhibiting the integrator circuit after the delivery of the output signal. The refractory circuit is formed by a first MOS transistor having a first conduction-terminal coupled to a supply node, a second conduction-terminal coupled to a common node, and a control-terminal coupled to the output, and a second MOS transistor having a first conduction-terminal coupled to the input, a second conduction-terminal coupled to a reference node at which a reference voltage is received, and a control-terminal coupled to the common node. A resistive-capacitive circuit is coupled between the supply node and the reference node and having a tap coupled to the common node, with the inhibition duration being dependent upon a time constant of the resistive-capacitive circuit.

Amplifier having electrostatic discharge and surge protection circuit. In some embodiments, a radio-frequency integrated circuit can include an amplifier, a controller configured to control operation of the amplifier, and a clamp circuit configured to provide electrostatic discharge protection and surge protection for either or both of the amplifier and the controller. The clamp circuit can include a feedback combination clamp implemented to direct a current associated with either or both of an electrostatic discharge and a surge at a first node to a second node.

A device is disclosed herein. The device includes an electrostatic discharge (ESD) protection switch and an ESD driver. The ESD driver is configured to receive a first voltage and a second voltage. When a voltage difference between the first voltage and the second voltage is higher than a first voltage threshold, the ESD driver outputs a first trigger signal to turn on the ESD protection switch. When the voltage difference between the first voltage and the second voltage is lower than a second voltage threshold, the ESD driver outputs a second trigger signal to turn on the ESD protection switch.