An enhancement-mode (e-mode) field effect transistor (FET) comprises a buffer layer, and a superlattice of conducting channels on the buffer layer and including a trench that cuts down through the superlattice into the buffer layer and separates the superlattice into a source-access region and a drain-access region, wherein the buffer layer forms a bottom of the trench. The e-mode FET includes a source and a drain adjacent to the source-access region and the drain-access region, respectively. The e-mode FET further includes a gate in the trench, such that a voltage above a threshold voltage of the e-mode FET applied to the gate induces a current channel in the buffer layer underneath the gate, which electrically connects the source-access region to the drain-access region to turn on the e-mode FET, and (ii) a voltage below the threshold voltage applied to the gate eliminates the current channel, which electrically disconnects the source-access region from the drain-access region to turn off the e-mode FET.

Disclosed herein are IC structures, packages, and devices that include self-aligned III-N transistors monolithically integrated on the same support structure or material (e.g., a substrate, a die, or a chip) as extended-drain III-N transistors. Self-aligned III-N transistors may provide a viable approach to implementing digital logic circuits, e.g., to implementing enhancement mode transistors, on the same support structure with extended-drain III-N transistors which may be used as high-power transistors used to implement various RF components, thus enabling integration of III-N devices with digital logic.

Novel and useful quantum structures that provide various control functions. Particles are brought into close proximity to interact with one another and exchange information. After entanglement, the particles are moved away from each other but they still carry the information contained initially. Measurement and detection are performed on the particles from the entangled ensemble to determine whether the particle is present or not in a given qdot. A quantum interaction gate is a circuit or structure operating on a relatively small number of qubits. Quantum interaction gates implement several quantum functions including a controlled NOT gate, quantum annealing gate, controlled SWAP gate, a controlled Pauli rotation gate, and ancillary gate. These quantum interaction gates can have numerous shapes including double V shape, H shape, X shape, L shape, I shape, etc.

A novel and useful controlled quantum shift register for transporting particles from one quantum dot to another in a quantum structure. The shift register incorporates a succession of qdots with tunneling paths and control gates. Applying appropriate control signals to the control gates, a particle or a split quantum state is made to travel along the shift register. The shift register also includes ancillary double interaction where two pairs of quantum dots provide an ancillary function where the quantum state of one pair is replicated in the second pair. The shift register also provides bifurcation where an access path is split into two or more paths. Depending on the control pulse signals applied, quantum dots are extended into multiple paths. Control of the shift register is provided by electric control pulses. An optional auxiliary magnetic field provides additional control of the shift register.

A gallium nitride based monolithic microwave integrated circuit includes a substrate, a channel layer on the substrate and a barrier layer on the channel layer. A recess is provided in a top surface of the barrier layer. First gate, source and drain electrodes are provided on the barrier layer opposite the channel layer, with a bottom surface of the first gate electrode in direct contact with the barrier layer. Second gate, source and drain electrodes are also provided on the barrier layer opposite the channel layer. A gate insulating layer is provided in the recess in the barrier layer, and the second gate electrode is on the gate insulating layer opposite the barrier layer and extending into the recess. The first gate, source and drain electrodes comprise the electrodes of a depletion mode transistor, and the second gate, source and drain electrodes comprise the electrodes of an enhancement mode transistor.

A reference voltage generation device (100) includes a constant current circuit (101) configured to output a constant current; and a plurality of voltage generation circuits (102) each configured to generate an output voltage based on the constant current, wherein the constant current has a correlation represented by a first gradient with respect to a temperature change, and wherein a plurality of the output voltages from the plurality of voltage generation circuits (102) have correlations represented by second gradients that are inverse to the correlation represented by the first gradient with respect to the temperature change and have different gradient indices. The reference voltage generation device (100) is configured to generate a reference voltage based on the constant current and the output voltage of at least one voltage generation circuit selected from the plurality of voltage generation circuits.

A monolithic integration of enhancement mode (E-mode) and depletion mode (D-mode) field effect transistors (FETs) comprises a compound semiconductor substrate overlaid by an epitaxial structure overlaid by source and drain electrodes. The epitaxial structure includes from bottom to top sequentially a buffer layer, a channel layer, a Schottky barrier layer, a first etch stop layer, and a first cap layer. The respective first gate metal layers of the D-mode and E-mode FET are in contact with the first etch stop layer. The D-mode and E-mode gate-sinking regions are beneath the respective first gate metal layers of the D-mode and E-mode gate electrode at least within the first etch stop layer. The first gate metal layer material of the D-mode is the same as that of the E-mode, where the first gate metal layer thickness of the E-mode is greater than that of the D-mode.

An integrated enhancement/depletion mode high electron mobility transistor (HEMT) includes a substrate, a buffer layer, a first barrier layer, a second barrier layer, a first source, a first drain a first gate, a second source, a second drain, and a second gate. The buffer layer is on the substrate. The first barrier layer is on the buffer layer, and the second barrier layer is on the first barrier layer. The second barrier layer covers a portion of the first barrier layer. The first source, the first drain, and the first gate are on the first barrier layer, and the second source, the second drain, and the second gate are on the second banner layer.

An integrated enhancement/depletion mode high electron mobility transistor (HEMT) includes a substrate, a first buffer layer, a first barrier layer, a first channel layer, a first source, a first drain, a first gate, a second buffer layer, a second barrier layer, a second channel layer, a second source, a second drain, and a second gate. The first buffer layer is on the substrate. The first barrier layer is on a first area of the first buffer layer, the first channel layer is on the first barrier layer, and the first source, the first drain, and the first gate are on the first channel layer. The second buffer layer is on a second area of the first buffer layer, the second bather layer is on the second buffer layer, the second channel layer is on the second barrier layer, and the second source, the second drain, and the second gate are on the second channel layer.

A method of forming an integrated circuit can include forming a heterostructure over a substrate structure, wherein the given substrate structure comprises a given semiconductor material. The method can include etching a castellated channel region in an e-mode device area of the heterostructure that defines a plurality of ridge channels interleaved between a plurality of trenches, the ridge channels comprising another semiconductor material. The method can also include forming an isolation region on the heterostructure to electrically isolate the e-mode device area from a d-mode device area of the heterostructure. The method can further include forming a mask with an opening that defines a castellated gate opening overlying the castellated channel region and the mask defines an opening overlaying a single planar gate overlying the d-mode device area of the heterostructure. The method can also include performing a contact fill with conductive material to form a castellated gate contact.