A semiconductor device includes transistor cells and enhancement cells. Each transistor cell includes a body zone that forms a first pn junction with a drift structure. The transistor cells may form, in the body zones, inversion channels when a first control signal exceeds a first threshold. The inversion channels form part of a connection between the drift structure and a first load electrode. A delay unit generates a second control signal which trailing edge is delayed with respect to a trailing edge of the first control signal. The enhancement cells form inversion layers in the drift structure when the second control signal falls below a second threshold lower than the first threshold. The inversion layers are effective as minority charge carrier emitters.

A reference voltage circuit includes a first MOS transistor pair having a first MOS transistor of an enhancement type having a gate and a drain connected to each other, and a second MOS transistor of a depletion type having a gate connected to a source of the first MOS transistor, a source connected to the drain of the first MOS transistor, and a drain connected to an output terminal; and a second MOS transistor pair having a third MOS transistor of an enhancement type having a gate and a drain connected to the output terminal and a source connected to the source of the second MOS transistor, and a fourth MOS transistor of a depletion type having a gate connected to the source of the third MOS transistor and a source connected to the output terminal. All the MOS transistors operate in a weak inversion region.

Novel and useful quantum structures that provide various control functions. Particles are brought into close proximity to interact with one another and exchange information. After entanglement, the particles are moved away from each other but they still carry the information contained initially. Measurement and detection are performed on the particles from the entangled ensemble to determine whether the particle is present or not in a given qdot. A quantum interaction gate is a circuit or structure operating on a relatively small number of qubits. Quantum interaction gates implement several quantum functions including a controlled NOT gate, quantum annealing gate, controlled SWAP gate, a controlled Pauli rotation gate, and ancillary gate. These quantum interaction gates can have numerous shapes including double V shape, H shape, X shape, L shape, I shape, etc.

A semiconductor device and a fabricating method thereof are provided. The semiconductor device includes a substrate, a first nanowire spaced apart from a first region of the substrate, a first gate electrode surrounding a periphery of the first nanowire, a second nanowire spaced apart from a second region of the substrate and extending in a first direction and having a first width in a second direction intersecting the first direction, a supporting pattern contacting the second nanowire and positioned under the second nanowire, and a second gate electrode extending in the second direction and surrounding the second nanowire and the supporting pattern.

A semiconductor device includes etch stop films formed on the first gate electrode, the first source region, the first drain region, and the shallow trench isolation regions, respectively. First interlayer insulating films are formed on the etch stop film, respectively. Deep trenches are formed in the substrate between adjacent ones of the first interlayer insulating films to overlap the shallow trench isolation regions. Sidewall insulating films are formed in the deep trenches, respectively. A gap-fill insulating film is formed on the sidewall insulating film. A second interlayer insulating film is formed on the gap-fill insulating film. A top surface of the second interlayer insulating film is substantially planar and a bottom surface of the second interlayer insulating film is undulating.

A semiconductor device includes a substrate (110); a buried layer (120) formed on the substrate (110), a diffusion layer (130) formed on the buried layer (120), wherein the diffusion layer (130) includes a first diffusion region (132) and a second diffusion region (134), and an impurity type of the second diffusion region (134) is opposite to an impurity type of the first diffusion region (132); the diffusion layer (134) further comprises a plurality of third diffusion regions (136) formed in the second diffusion region, wherein an impurity type of the third diffusion region (136) is opposite to the impurity type of the second diffusion region (134); and a gate (144) formed on the diffusion layer (130).

A semiconductor device includes a first semiconductor region of a first conductivity type, second, third and fourth semiconductor regions of a second conductivity type, a first insulating film, a second insulating film, a first electrode contacting the first insulating film, and a second electrode contacting the second insulating film. The second and third semiconductor regions contact the first semiconductor region. The fourth semiconductor region contacts the first semiconductor region, is disposed between the second semiconductor region and the third semiconductor region. The first insulating film contacts a first portion of the first semiconductor region between the second semiconductor region and the fourth semiconductor region. The second insulating film contacts a second portion of the first semiconductor region between the third semiconductor region and the fourth semiconductor region. The second insulating film is thicker than the first insulating film.

We disclose a III-nitride semiconductor based heterojunction power device, comprising: a first heterojunction transistor formed on a substrate, the first heterojunction transistor comprising: a first III-nitride semiconductor region formed over the substrate, wherein the first III-nitride semiconductor region comprises a first heterojunction comprising at least one two dimensional carrier gas of second conductivity type; a first terminal operatively connected to the first III-nitride semiconductor region; a second terminal laterally spaced from the first terminal and operatively connected to the first III-nitride semiconductor region; a first gate terminal formed over the first III-nitride semiconductor region between the first terminal and the second terminal. The device also includes a second heterojunction transistor formed on a substrate, the second heterojunction transistor comprising: a second III-nitride semiconductor region formed over the substrate, wherein the second III-nitride semiconductor region comprises a second heterojunction comprising at least one two dimensional carrier gas of second conductivity type; a third terminal operatively connected to the second III-nitride semiconductor region; a fourth terminal laterally spaced from the third terminal in a first dimension and operatively connected to the second III-nitride semiconductor region, wherein the fourth terminal is operatively connected to the first gate terminal; and a second gate terminal formed over the second III-nitride semiconductor region between the third terminal and the fourth terminal and wherein the second heterojunction transistor is used in sensing and protection functions of the first power heterojunction transistor.

The present application provides an integrated semiconductor device and an electronic apparatus, comprising a semiconductor substrate and a first doped epitaxial layer having a first region, a second region, and a third region; a partition structure is arranged in the third region; the first region is formed having at least two second doped deep wells, and the second region is formed having at least two second doped deep wells; a dielectric island partially covers a region between two adjacent doped deep wells in the first region and second region; a gate structure covers the dielectric island; a first doped source region is located on the two sides of the gate structure, and a first doped source region located in the same second doped deep well is separated; a first doped trench is located on the two sides of the dielectric island in the first region, and extends laterally to the first doped source region.

The disclosure relates to a III-nitride power semiconductor based heterojunction device including a low voltage terminal, a high voltage terminal, a control terminal and an active heterojunction transistor formed on a substrate, and further including the following monolithically integrated components: voltage clamp circuit configured to limit a maximum potential that can be applied to the internal gate terminal, an on-state circuit configured to control the internal gate terminal of the active heterojunction transistor during an on-state operation, a turn-off circuit configured to control the internal gate terminal of the active heterojunction transistor during a turn-off operation and during an off-state.