In an embodiment, an integrated circuit includes transistors in different active regions, electrically isolated using single diffusion break isolation. The single diffusion break isolation includes a first dummy transistor that has a different threshold voltage than the transistors in either active region for which the single diffusion break is creating isolation. The first dummy transistor may have lower leakage current than transistors in either active region, creating effective isolation between the active regions and consuming relatively small amounts of power due to the lower leakage currents.

A semiconductor device is made by: forming a metal film containing Al on a surface of a substrate product including a substrate and a nitride semiconductor layer on the substrate, the metal film covering a via hole forming predetermined region, and the surface of the substrate product being located on the nitride semiconductor layer side, forming an etching mask having an opening for exposing the via hole forming predetermined region on a back surface of the substrate product, the back surface of the substrate product being located on the substrate side, and forming a via hole in the substrate product by reactive ion etching, the via hole reaching the surface from the back surface and exposing the metal film. In the forming of the via hole, a reaction gas containing fluorine is used during a period at least including a termination of etching.

The present invention relates to an epitaxial structure of N-face group III nitride, its active device, and its gate protection device. The epitaxial structure of N-face AlGaN/GaN comprises a silicon substrate, a buffer layer (C-doped) on the silicon substrate, an i-GaN (C-doped) layer on the buffer layer (C-doped), an i-Al.sub.yGaN buffer layer on the i-GaN (C-doped) layer, an i-GaN channel layer on the i-Al.sub.yGaN buffer layer, and an i-Al.sub.xGaN layer on the i-GaN channel layer, where x=0.1˜0.3 and y=0.05˜0.75. By connecting a depletion-mode (D-mode) AlGaN/GaN high electron mobility transistor (HEMT) to the gate of a p-GaN gate enhancement-mode (E-mode) AlGaN/GaN HEMT in device design, the gate of the p-GaN gate E-mode AlGaN/GaN HEMT can be protected under any gate voltage.

A semiconductor device and a fabricating method thereof are provided. The semiconductor device includes a substrate, a first nanowire spaced apart from a first region of the substrate, a first gate electrode surrounding a periphery of the first nanowire, a second nanowire spaced apart from a second region of the substrate and extending in a first direction and having a first width in a second direction intersecting the first direction, a supporting pattern contacting the second nanowire and positioned under the second nanowire, and a second gate electrode extending in the second direction and surrounding the second nanowire and the supporting pattern.

A III-nitride semiconductor based heterojunction power device including: a first heterojunction transistor formed on a substrate, and a second heterojunction transistor formed on the substrate. One of the first heterojunction transistor and the second heterojunction transistor is an enhancement mode field effect transistor and the other one of the first heterojunction transistor and the second heterojunction transistor is a depletion mode field effect transistor. The enhancement mode transistor acts as a main power switch, and the depletion mode transistor acts as a start-up component.

A semiconductor device includes etch stop films formed on the first gate electrode, the first source region, the first drain region, and the shallow trench isolation regions, respectively. First interlayer insulating films are formed on the etch stop film, respectively. Deep trenches are formed in the substrate between adjacent ones of the first interlayer insulating films to overlap the shallow trench isolation regions. Sidewall insulating films are formed in the deep trenches, respectively. A gap-fill insulating film is formed on the sidewall insulating film. A second interlayer insulating film is formed on the gap-fill insulating film. A top surface of the second interlayer insulating film is substantially planar and a bottom surface of the second interlayer insulating film is undulating.

A protection circuit includes a first PMOS and a first PDMOS receiving input of voltage of a voltage dividing point of voltage input from an external power supply terminal, and a second PMOS and a second PDMOS receiving input of drain output voltage of the first PDMOS. The first PMOS is connected on the external power supply terminal side of the first PDMOS, and the second PMOS is connected on the external power supply terminal side of the second PDMOS. During overvoltage application, the voltage of the voltage dividing point is clamped to the breakdown voltage of a Zener diode, the second PDMOS turns OFF, and supply to an integrated circuit protected from overvoltage is cut off. When the voltage source is connected in reverse, parasitic diodes of the first and second PMOSs are reverse-biased and the flow of current in a path through the parasitic diodes is inhibited.

The present invention provides an epitaxial structure of Ga-face group III nitride, its active device, and the method for fabricating the same. The epitaxial structure of Ga-face AlGaN/GaN comprises a substrate, an i-GaN (C-doped) layer on the substrate, an i-Al(y)GaN buffer layer on the i-GaN (C-doped) layer, an i-GaN channel layer on the i-Al(y)GaN buffer layer, and an i-Al(x)GaN layer on the i-GaN channel layer, where x=0.1˜0.3 and y=0.05˜0.75. By using the p-GaN inverted trapezoidal gate or anode structure in device design, the 2DEG in the epitaxial structure of Ga-face group III nitride below the p-GaN inverted trapezoidal structure will be depleted, and thus fabricating p-GaN gate enhancement-mode (E-mode) AlGaN/GaN high electron mobility transistors (HEMTs), p-GaN anode AlGaN/GaN Schottky barrier diodes (SBDs), or hybrid devices.

Apparatus and circuits including transistors with different threshold voltages and methods of fabricating the same are disclosed. In one example, a semiconductor structure is disclosed. The semiconductor structure includes: a substrate; an active layer that is formed over the substrate and comprises a plurality of active portions; a polarization modulation layer comprising a plurality of polarization modulation portions each of which is disposed on a corresponding one of the plurality of active portions; and a plurality of transistors each of which comprises a source region, a drain region, and a gate structure formed on a corresponding one of the plurality of polarization modulation portions. The transistors have at least three different threshold voltages.

A process for manufacturing an integrated circuit (IC) with a through via extending through a group III-V layer to a diode is provided. An etch is performed through the group III-V layer, into a semiconductor substrate underlying the group III-V layer, to form a via opening. A doped region is formed in the semiconductor substrate, through the via opening. Further, the doped region is formed with an opposite doping type as a surrounding region of the semiconductor substrate. The through via is formed in the via opening and in electrical communication with the doped region.