A semiconductor structure includes a metal gate structure (MG) formed over a substrate, a first gate spacer formed on a first sidewall of the MG, a second gate spacer formed on a second sidewall of the MG opposite to the first sidewall, where the second gate spacer is shorter than the first gate spacer, a source/drain (S/D) contact (MD) adjacent to the MG, where a sidewall of the MD is defined by the second gate spacer, and a contact feature configured to electrically connect the MG to the MD.

A semiconductor structure includes a first device and a second device. The first device includes: a first gate structure formed over an active region and a first air spacer disposed adjacent to the first gate structure. The second device includes: a second gate structure formed over an isolation structure and a second air spacer disposed adjacent to the second gate structure. The first air spacer and the second air spacer have different sizes.

An IC structure includes first, second, third, and fourth transistors on a substrate, a first net and a second net. The first net includes a plurality of first metal lines routed on a first metallization layer, and a plurality of first metal vias electrically connecting the plurality of first metal lines to the first and second transistors. The second net includes a plurality of second metal lines routed on a second metallization layer, and a plurality of second metal vias electrically connecting the plurality of second metal lines to the third and fourth transistors. A total length of the second metal lines of the second net is shorter than a total length of the first metal lines of the first net. A count of the f first metal vias of the first net is less than a count of the second metal vias of the second net.

A semiconductor structure and a method for forming the same are provided. In one form, the method includes: providing a base, a gate structure being formed on the base, a source/drain doped layer being formed within the base on both sides of the gate structure, and an initial dielectric layer being formed on the base exposed from the gate structure, the initial dielectric layer covering a top of the gate structure, and a source/drain contact plug electrically connected to the source/drain doped layer being formed within the initial dielectric layer on the top of the source/drain doped layer; removing a portion of a thickness of the initial dielectric layer to form a dielectric layer exposing a portion of a side wall of the source/drain contact plug; forming an etch stop layer on at least the side wall of source/drain contact plug exposed from the dielectric layer; etching the dielectric layer on the top of the gate structure using etch stop layers on side walls of adjacent source/drain contact plugs as lateral stop positions, to form a gate contact exposing the top of the gate structure; forming, within the gate contact, a gate contact plug electrically connected to the gate structure. Implementations of the present disclosure facilitate enlargement of a process window for forming a contact over active gate.

Semiconductor device structures are provided. The semiconductor device structure includes a substrate and a first fin structure protruding from the substrate. The semiconductor device structure further includes a gate stack formed across the first fin structure and a first source/drain structure formed over the first fin structure adjacent to the gate stack. The semiconductor device structure further includes a contact structure formed over the first source/drain structure and a dielectric structure formed through the contact structure. In addition, a bottom surface of the contact structure is wider than a top surface of the contact structure.

A semiconductor device includes first well regions in a substrate and spaced apart from each other, a connection doped region between the first well regions, and a first interconnection line electrically connected to the connection doped region through a first contact. The first well regions and the connection doped region include impurities of a first conductivity type, and a concentration of the impurities in the connection doped region is higher than that in the first well regions. The first well regions extend into the substrate to a depth larger than that of the connection doped region. A first portion of the connection doped region is disposed in the first well regions and a second portion of the connection doped region contacts the substrate.

Described herein are transistor arrangements fabricated by forming a metal gate cut as a trench that is non-selective to the gate sidewalls, in an etch process that can remove both the gate electrode materials and the surrounding dielectrics. Such an etch process may provide improvements in terms of accuracy, cost-efficiency, and device performance, compared to conventional approaches to forming metal gate cuts. In addition, such a process may be used to provide power rails, if the trench of a metal gate cut is to be at least partially filled with an electrically conductive material. Because the electrically conductive material is in the trench and may be in between the fins, as opposed to being provided over the fins, such power rails may be referred to as “recessed.” Providing recessed power rails may provide improvements in terms of reduced metal line resistance and reduced voltage droop.

A semiconductor device structure is provided. The semiconductor device structure includes a first stacked nanostructure and a second stacked nanostructure formed over a substrate, and a dummy fin structure between the first stacked nanostructure and the second stacked nanostructure. The semiconductor device structure includes a gate structure formed over the first stacked nanostructure and the second stacked nanostructure, and a conductive layer formed over the gate structure. The semiconductor device structure includes a capping layer formed over the dummy fin structure, and each of the gate structure and the conductive layer is divided into two portions by the capping layer.

In a method of manufacturing a semiconductor device, a separation wall made of a dielectric material is formed between two fin structures. A dummy gate structure is formed over the separation wall and the two fin structures. An interlayer dielectric (ILD) layer is formed over the dummy gate structure. An upper portion of the ILD layer is removed, thereby exposing the dummy gate structure. The dummy gate structure is replaced with a metal gate structure. A planarization operation is performed to expose the separation wall, thereby dividing the metal gate structure into a first gate structure and a second gate structure. The first gate structure and the second gate structure are separated by the separation wall.

The present disclosure describes a method to form silicon germanium (SiGe) source/drain epitaxial stacks with a boron doping profile and a germanium concentration that can induce external stress to a fully strained SiGe channel. The method includes forming one or more gate structures over a fin, where the fin includes a fin height, a first sidewall, and a second sidewall opposite to the first sidewall. The method also includes forming a first spacer on the first sidewall of the fin and a second spacer on the second sidewall of the fin; etching the fin to reduce the fin height between the one or more gate structures; and etching the first spacer and the second spacer between the one or more gate structures so that the etched first spacer is shorter than the etched second spacer and the first and second etched spacers are shorter than the etched fin. The method further includes forming an epitaxial stack on the etched fin between the one or more gate structures.