Embodiments of the present disclosure provide methods for forming merged source/drain features from two or more fin structures. The merged source/drain features according to the present disclosure have a merged portion with an increased height percentage over the overall height of the source/drain feature. The increase height percentage provides an increased landing range for source/drain contact features, therefore, reducing the connection resistance between the source/drain feature and the source/drain contact features. In some embodiments, the emerged source/drain features include one or more voids formed within the merged portion.

A semiconductor device structure, along with methods of forming such, are described. In one embodiment, a semiconductor device structure is provided. The semiconductor device structure a first source/drain region, a second source/drain region, and a gate stack disposed between the first source/drain region and the second source/drain region. The semiconductor device structure also includes a conductive feature disposed below the first source/drain region. The semiconductor device structure also includes a power rail disposed below and in contact with the conductive feature. semiconductor device structure also includes a dielectric layer enclosing the conductive feature, wherein an air gap is formed between the dielectric layer and the conductive feature.

A semiconductor device includes a substrate, a semiconductor fin, a shallow trench isolation (STI) structure, an air spacer, and a gate structure. The semiconductor fin extends upwardly from the substrate. The STI structure laterally surrounds a lower portion of the semiconductor fin. The air spacer is interposed the STI structure and the semiconductor fin. The gate structure extends across the semiconductor fin.

An integrated circuit structure includes a substrate, a transistor, a first dielectric layer, a metal contact, a first low-k dielectric layer, a second dielectric layer, and a first metal feature. The transistor is over the substrate. The first dielectric layer is over the transistor. The metal contact is in the first dielectric layer and electrically connected to the transistor. The first low-k dielectric layer is over the first dielectric layer. The second dielectric layer is over the first low-k dielectric layer and has a dielectric constant higher than a dielectric constant of the first low-k dielectric layer. The first metal feature extends through both second dielectric layer and the first low-k dielectric layer to the metal contact.

Provided are methods of manufacturing an integrated circuit device including depositing a conductive layer on a substrate, patterning the conductive layer to expose regions of the conductive layer, etching a first portion of the exposed regions of the conductive layer, forming a first passivation layer on a sidewall of the first etched portion, etching a second portion of the exposed regions of the conductive layer, and forming a second passivation layer on a sidewall of the second etched portion.

Embodiments provide a dielectric inter block disposed in a metallic region of a conductive line or source/drain contact. A first and second conductive structure over the metallic region may extend into the metallic region on either side of the inter block. The inter block can prevent etchant or cleaning solution from contacting an interface between the first conductive structure and the metallic region.

Gate aligned contacts and methods of forming gate aligned contacts are described. For example, a method of fabricating a semiconductor structure includes forming a plurality of gate structures above an active region formed above a substrate. The gate structures each include a gate dielectric layer, a gate electrode, and sidewall spacers. A plurality of contact plugs is formed, each contact plug formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. A plurality of contacts is formed, each contact formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. The plurality of contacts and the plurality of gate structures are formed subsequent to forming the plurality of contact plugs.

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having channel structures with sub-fin dopant diffusion blocking layers are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. The lower fin portion includes a dopant diffusion blocking layer on a first semiconductor layer doped to a first conductivity type. The upper fin portion includes a portion of a second semiconductor layer, the second semiconductor layer on the dopant diffusion blocking layer. An isolation structure is along sidewalls of the lower fin portion. A gate stack is over a top of and along sidewalls of the upper fin portion, the gate stack having a first side opposite a second side. A first source or drain structure at the first side of the gate stack.

Semiconductor device having less defects in a gate insulating film and improved reliability and methods of forming the semiconductor devices are provided. The semiconductor devices may include a gate insulating film on a substrate and a gate electrode structure on the gate insulating film. The gate electrode structure may include a lower conductive film, a silicon oxide film, and an upper conductive film sequentially stacked on the gate insulating film. The lower conductive film may include a barrier metal layer.

An integrated circuit includes a substrate, an isolation feature disposed over the substrate, a fin extending from the substrate alongside the isolation feature such that the fin extends above the isolation feature, and a dielectric layer disposed over the isolation feature. A top surface of the dielectric layer is at a same level as a top surface of the fin or below a top surface of the fin by less than or equal to 15 nanometers.