Semiconductor devices and methods of manufacturing are provided. In some embodiments the method includes depositing an etch stop layer over a first hard mask material, the first hard mask material over a gate stack, depositing an interlayer dielectric over the etch stop layer, forming a first opening through the interlayer dielectric, the etch stop layer, and the first hard mask material, the first opening exposing a conductive portion of the gate stack, and treating sidewalls of the first opening with a first dopant to form a first treated region within the interlayer dielectric, a second treated region within the etch stop layer, a third treated region within the first hard mask material, and a fourth treated region within the conductive portion, wherein after the treating the fourth treated region has a higher concentration of the first dopant than the first treated region.

A semiconductor device includes an active region that extends in a first horizontal direction. A source/drain component is disposed over the active region. A source/drain contact is disposed over the source/drain component. A gate structure is disposed over the active region. The gate structure extends in a second horizontal direction different from the first horizontal direction. Side surfaces of the source/drain contact are substantially more tapered in the second horizontal direction than in the first horizontal direction.

A semiconductor device includes a first active fin protruding from a substrate, a first gate pattern covering a side surface and a top surface of the first active fin, and first source/drain patterns at opposite sides of the first gate pattern, each of the first source/drain patterns including a first lower side and a second lower side spaced apart from each other, a first upper side extended from the first lower side, a second upper side extended from the second lower side. The first lower side may be inclined at a first angle relative to a top surface of the substrate, the second upper side may be inclined at a second angle relative to the top surface of the substrate, and the first angle may be greater than the second angle.

A semiconductor device and method of manufacturing the semiconductor device are provided. An exemplary semiconductor device comprises a fin disposed over a substrate, wherein the fin includes a channel region and a source/drain region; a gate structure disposed over the substrate and over the channel region of the fin; a source/drain feature epitaxially grown in the source/drain region of the fin, wherein the source/drain feature includes a top epitaxial layer and a lower epitaxial layer formed below the top epitaxial layer, and the lower epitaxial layer includes a wavy top surface; and a contact having a wavy bottom surface matingly engaged with the wavy top surface of the lower epitaxial layer of the source/drain feature.

An electronic system may include one or more units of processing circuitry configured to implement a main intellectual property (IP), a checker IP, and an error detection circuit. The main IP includes a first data path and a first control signal path. The checker IP includes a second control signal path. The error detection circuit is configured to detect an error of data by performing error correction code (ECC) decoding of output data that is output by the main IP to the error detection circuit through the first data path, and detect an error of a control signal based on a first signal that is output by the main IP to the error detection circuit through the first control signal path, and a second signal that is output by the checker IP to the error detection circuit through the second control signal path.

Embodiments of the present disclosure provide a method for forming backside metal contacts with reduced C.sub.gd and increased speed. Particularly, source/drain features on the drain side, or source/drain features without backside metal contact, are recessed from the backside to the level of the inner spacer to reduce C.sub.gd. Some embodiments of the present disclosure use a sacrificial liner to protect backside alignment feature during backside processing, thus, preventing shape erosion of metal conducts and improving device performance.

A method includes forming a first dielectric layer over a source/drain region, and forming a source/drain contact plug over and electrically connecting to the source/drain region. A top portion of the source/drain contact plug has a first lateral dimension. An implantation process is performed to implant a dopant into the first dielectric layer. The implantation process results in the source/drain contact plug to have a second lateral dimension smaller than the first lateral dimension. The method further includes forming a second dielectric layer over the etch stop layer, and forming a gate contact plug adjacent to the source/drain contact plug.

A semiconductor device including a test structure includes a semiconductor substrate and a plurality of test structures on the semiconductor substrate. The test structures include respective lower active regions extending from the semiconductor substrate in a vertical direction and having different widths, and upper active regions extending from respective lower active regions in the vertical direction. Each of the lower active regions includes first regions and second regions. The first regions overlap the upper active regions and are between the second regions, and the second regions include outer regions and inner regions between the outer regions. The outer regions, located in the lower active regions having different widths, have different widths.

A semiconductor device includes a substrate, a gate structure on the substrate and a first conductive connection group on the gate structure. The gate structure includes a gate spacer and a gate electrode. The first conductive connection group includes a ferroelectric material layer. At least a part of the ferroelectric material layer is disposed above an upper surface of the gate spacer. And the ferroelectric material layer forms a ferroelectric capacitor having a negative capacitance in the first conductive connection group.

The disclosed technology relates generally to semiconductor devices and manufacturing methods thereof, and more particularly to field-effect transistors operating at different voltages and methods for integrating the same. In one aspect, a method of fabricating a semiconductor device comprises: a) providing a substrate and a first hardmask; b) next, providing a second hardmask over a first region of the first hardmask; c) next, forming a first set of hardmask fins in a second region of the first hardmask; d) next, masking the second region; e) next, providing a set of photoresist fins on the second hardmask; f) next, patterning the second hardmask and the first region by using the photoresist fins as a mask; g) next, forming a first set of semiconductor fins of a first height by etching the substrate; h) next, removing the mask provided in step d; i) next, forming a second set of semiconductor fins of a second height in the second region and extending the height of the first set of semiconductor fins to a third height in the first region, by etching the substrate by using the first and second sets of hardmask fins as masks.