A semiconductor device includes a first fin type pattern in a first region of a substrate. The first fin type pattern includes a plurality of spaced-apart fins having respective sidewalls defined by a first trench. A first gate structure is provided, which intersects the first fin type pattern. A second fin type pattern is provided in a second region of a substrate. The second fin type pattern includes a fin having a sidewall defined by a second trench. A second gate structure is provided, which intersects the second fin type pattern. A field insulating film fills at least a part of the first trench and at least a part of the second trench. The field insulating film has a first upper surface, which is in contact with at least one sidewall of the first fin type pattern and is spaced from a bottom of the first trench by a first height, and a second upper surface, which in contact with the sidewall of the second fin type pattern and is spaced from a bottom of the second trench by a second height different from the first height.

A semiconductor device and a method for forming the semiconductor device are provided. The method includes providing a substrate; forming a fin on the substrate, where the substrate includes a fin dense region and a fin sparse region; forming a gate structure across the fin over the substrate; forming a source-drain doped layer in the fin on both sides of the gate structure; forming a dielectric layer over the substrate, where the dielectric layer covers a top of the gate structure; and forming a first through-hole in the dielectric layer on a side of the gate structure in the fin sparse region, where a bottom of the first through-hole exposes a top sidewall of the gate structure.

A semiconductor structure includes a field effect transistor (FET) having a source/drain, a contact in contact with the source/drain, and a buried power rail including a conductive material, wherein the buried power rail is in contact with the contact, wherein a first portion of the buried power rail closest to the contact has a first thickness, and wherein a second portion of the buried power rail has a second thickness such that the first thickness is less than the second thickness.

A method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming isolation regions on opposing sides of the fin; forming a dummy gate over the fin; reducing a thickness of a lower portion of the dummy gate proximate to the isolation regions, where after reducing the thickness, a distance between opposing sidewalls of the lower portion of the dummy gate decreases as the dummy gate extends toward the isolation regions; after reducing the thickness, forming a gate fill material along at least the opposing sidewalls of the lower portion of the dummy gate; forming gate spacers along sidewalls of the dummy gate and along sidewalls of the gate fill material; and replacing the dummy gate with a metal gate.

Discussed herein is gate spacing in integrated circuit (IC) structures, as well as related methods and components. For example, in some embodiments, an IC structure may include: a first gate metal having a longitudinal axis; a second gate metal, wherein the longitudinal axis of the first gate metal is aligned with a longitudinal axis of the second gate metal; a first dielectric material continuously around the first gate metal; and a second dielectric material continuously around the second gate metal, wherein the first dielectric material and the second dielectric material are present between the first gate metal and the second gate metal.

A semiconductor structure includes a semiconductor substrate containing a shallow trench isolation structure that laterally surrounds a transistor active region, at least one line trench vertically extending into the semiconductor substrate, and a source region and a drain region located in the transistor active region. A contoured channel region continuously extends from the source region to the drain region underneath the at least one line trench. A gate dielectric contacts all surfaces of the at least one line trench and extends over an entirety of the contoured channel region. A gate electrode containing at least one fin portion overlies the gate dielectric.

A field effect transistor includes at least one line trench extending downward from a top surface of a channel region which laterally surrounds or underlies the at least one line trench, a gate dielectric contacting all surfaces of the at least one line trench and including a planar gate dielectric portion that extends over an entirety of a top surface of the channel region, a gate electrode, a source region, and a drain region.

A semiconductor device includes; an active region extending in a first horizontal direction on a substrate, source/drain regions disposed on the active region, a buried trench formed between the source/drain regions, a buried insulating layer surrounding both side walls of the buried trench in the first horizontal direction between the source/drain regions, a wing trench formed in a lower part of the buried trench and having a width greater than a width of the buried trench, and a gate electrode extending in a second horizontal direction on the active region, and disposed within each of the buried trench and the wing trench.

A semiconductor device includes a substrate, a fin protruding from the substrate, and a gate stack over the substrate and engaging the fin. The fin having a first end and a second end. The semiconductor device also includes a dielectric layer abutting the first end of the fin and spacer features disposed on sidewalls of the gate stack and on a top surface of the dielectric layer.

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. An isolation structure surrounds a lower fin portion, the isolation structure comprising an insulating material having a top surface, and a semiconductor material on a portion of the top surface of the insulating material, wherein the semiconductor material is separated from the fin. A gate dielectric layer is over the top of an upper fin portion and laterally adjacent the sidewalls of the upper fin portion, the gate dielectric layer further on the semiconductor material on the portion of the top surface of the insulating material. A gate electrode is over the gate dielectric layer.