A semiconductor device and method of forming thereof includes a first fin and a second fin each extending from a substrate. A first gate segment is disposed over the first fin and a second gate segment is disposed over the second fin. An interlayer dielectric (ILD) layer is adjacent the first gate segment and the second gate segment. A cut region (e.g., opening or gap between first gate structure and the second gate structure) extends between the first and second gate segments. The cut region has a first portion has a first width and a second portion has a second width, the second width is greater than the first width. The second portion interposes the first and second gate segments and the first portion is defined within the ILD layer.

A semiconductor device including a gate separation region is provided. The semiconductor device includes an isolation region between active regions; interlayer insulating layers on the isolation region; gate line structures overlapping the active regions, disposed on the isolation region, and having end portions facing each other; and a gate separation region disposed on the isolation region, and disposed between the end portions of the gate line structures facing each other and between the interlayer insulating layers. The gate separation region comprises a gap fill layer and a buffer structure, the buffer structure includes a buffer liner disposed between the gap fill layer and the isolation region, between the end portions of the gate line structures facing each other and side surfaces of the gap fill layer, and between the interlayer insulating layers and the side surfaces of the gap fill layer.

A semiconductor device is provided. The semiconductor device includes a semiconductor fin over a substrate, and a gate structure along sidewalls and the top surface of the semiconductor fin. The gate structure covers the first portion of the semiconductor fin. The semiconductor device also includes a source/drain feature adjacent to the gate structure. The semiconductor device further includes a source/drain contact connected to the source/drain feature. The source/drain contact extends downwards to a position that is lower than the top surface of the first portion of the semiconductor fin.

A novel and useful quantum computing machine architecture that includes a classic computing core as well as a quantum computing core. A programmable pattern generator executes sequences of instructions that control the quantum core. In accordance with the sequences, a pulse generator functions to generate the control signals that are input to the quantum core to perform quantum operations. A partial readout of the quantum state in the quantum core is generated that is subsequently re-injected back into the quantum core to extend decoherence time. Access gates control movement of quantum particles in the quantum core. Errors are corrected from the partial readout before being re-injected back into the quantum core. Internal and external calibration loops calculate error syndromes and calibrate the control pulses input to the quantum core. Control of the quantum core is provided from an external support unit via the pattern generator or can be retrieved from classic memory where sequences of commands for the quantum core are stored a priori in the memory. A cryostat unit functions to provide several temperatures to the quantum machine including a temperature to cool the quantum computing core to approximately 4 Kelvin.

Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a fin disposed over a substrate, a gate structure disposed over a channel region of the fin, such that the gate structure traverses source/drain regions of the fin, a device-level interlayer dielectric (ILD) layer of a multi-layer interconnect structure disposed over the substrate, wherein the device-level ILD layer includes a first dielectric layer, a second dielectric layer disposed over the first dielectric layer, and a third dielectric layer disposed over the second dielectric layer, wherein a material of the third dielectric layer is different than a material of the second dielectric layer and a material of the first dielectric layer. The semiconductor device further comprises a gate contact to the gate structure disposed in the device-level ILD layer and a source/drain contact to the source/drain regions disposed in the device-level ILD layer.

A semiconductor device includes a substrate having first fin and a second fin spaced apart and extending lengthwise in parallel. A fin remnant is disposed between the first fin and the second fin, extends lengthwise in parallel with the first and second fins, and has a height lower than a height of each of the first fin and the second fin. A first field insulation layer is disposed between a sidewall of the first fin and a first sidewall of the fin remnant and a second field insulating layer is disposed on a sidewall of the second fin. A blocking liner conforms to a sidewall and a bottom surface of a trench bounded by a second sidewall of the fin remnant and a sidewall of the second field insulating layer. A trench insulation layer is disposed on the blocking liner in the trench.

Describe is a resonator that uses ferroelectric (FE) materials in the gate of a transistor as a dielectric. The use of FE increases the strain/stress generated in the gate of the FinFET. Along with the usual capacitive drive, which is boosted with the increased polarization, FE material expands or contacts depending on the applied electric field on the gate of the transistor. As such, acoustic waves are generated by switching polarization of the FE materials. In some embodiments, the acoustic mode of the resonator is isolated using phononic gratings all around the resonator using the metal line above and vias' to body and dummy fins on the side. As such, a Bragg reflector is formed above the FE based transistor.

A semiconductor device includes a single diffusion break (SDB) structure dividing a fin-shaped structure into a first portion and a second portion, an isolation structure on the SDB structure, a first spacer adjacent to the isolation structure, and a metal gate adjacent to the isolation structure. Preferably, a top surface of the first spacer is lower than a top surface of the isolation structure and a bottom surface of the first spacer is lower than a bottom surface of the metal gate.

A semiconductor device includes a lower wiring, an upper wiring on the lower wiring, and a via between the lower wiring and the upper wiring. The lower wiring has a first end surface and a second end surface opposing each other, the upper wiring has a third end surface and a fourth end surface opposing each other, and the via has a first side adjacent to the second end surface of the lower wiring and a second side adjacent to the third end surface of the upper wiring. A distance between a lower end of the first side of the via and an upper end of the second end surface of the lower wiring is less than ⅓ of a width of a top surface of the via, and a distance between an upper end of the second side of the via and an upper end of the third end surface of the upper wiring is less than ⅓ of the width of the top surface of the via.

An IC is provided. The IC includes a plurality of a plurality of P-type fin field-effect transistors (FinFETs). The P-type FinFETs includes at least one first P-type FinFET and at least one second P-type FinFET. Source/drain regions of the first P-type FinFET have a first depth, and source/drain regions of the second P-type FinFET have a second depth that is different from the first depth. A first semiconductor fin of the first P-type FinFET includes a first portion and a second portion that are formed by different materials, and the second portion of the first semiconductor fin has a third depth that is greater than the first depth.