A method of forming a semiconductor structure includes forming a first pattern of alternating spacers of a first material and a second material on a semiconductor substrate, forming a second pattern of the alternating spacers of the first material and the second material by selectively removing at least a portion of at least one of one or more of the spacers of the first material and one or more of the spacers of the second material to form a remaining pattern of spacers of the first material and the second material on the semiconductor substrate, and transferring the second pattern of the spacers of the first material and the second material to the semiconductor substrate to form two or more fins in the semiconductor substrate by etching the semiconductor substrate selective to the first material and the second material.

A method for forming a semiconductor device includes providing a substrate structure, which has a semiconductor substrate and a semiconductor fin on the substrate. The method also includes forming a catalytic material layer overlying the semiconductor fins, and forming an isolation region covering the catalytic material layer in a lower portion of the semiconductor fins. Next, a graphene nanoribbon is formed on the catalytic material layer on an upper portion of the semiconductor fin, and a gate structure is formed on the graphene nanoribbon.

The present disclosure provides many different embodiments of a FinFET device that provide one or more improvements over the prior art. In one embodiment, a FinFET includes a semiconductor substrate and a plurality of fins having a first height and a plurality of fin having a second height on the semiconductor substrate. The second height may be less than the first height.

A semiconductor arrangement and method of forming the same are described. A semiconductor arrangement includes a third metal connect in contact with a first metal connect in a first active region and a second metal connect in a second active region, and over a shallow trench isolation region located between the first active region and a second active region. A method of forming the semiconductor arrangement includes forming a first opening over the first metal connect, the STI region, and the second metal connect, and forming the third metal connect in the first opening. Forming the third metal connect over the first metal connect and the second metal connect mitigates RC coupling.

Semiconductor device fabrication method is provided. The method includes providing a substrate; forming a first semiconductor layer on the substrate; forming a stack of semiconductor layer structures on the first semiconductor layer, each of the semiconductor layer structures comprising a second semiconductor layer and a third semiconductor layer on the second semiconductor layer, the second and third semiconductor layers having at least a common compound element, and the third semiconductor layer and the first semiconductor layer having a same semiconductor compound; performing an etching process to form a fin structure; performing a selective etching process on the second semiconductor layer to form a first air gap between the first semiconductor layer and the third semiconductor layer and a second air gap between each of adjacent third semiconductor layers in the stack of one or more semiconductor layer structures; and filling the first and second air gaps with an insulator layer.

A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a first fin structure, a second fin structure, and a third fin structure over the semiconductor substrate. The semiconductor device structure also includes a merged semiconductor element on the first fin structure and the second fin structure and an isolated semiconductor element on the third fin structure. The semiconductor device structure further includes an isolation feature over the semiconductor substrate and partially or completely surrounding the first fin structure, the second fin structure, and the third fin structure. A top surface of the first fin structure is below a top surface of the isolation feature, and a top surface of the third fin structure is above the top surface of the isolation feature.

Integrated circuit devices include a substrate including first and second fin-type active regions and first and second gate structures. The first gate structure includes first gate insulating layer on the first fin-type active region to cover upper surface and both side surfaces of the first fin-type active region, first gate electrode on the first gate insulating layer and has first thickness in first direction perpendicular to upper surface of the substrate, and second gate electrode on the first gate electrode. The second gate structure includes second gate insulating layer on the second fin-type active region to cover upper surface and both side surfaces of the second fin-type active region, third gate insulating layer on the second gate insulating layer, third gate electrode on the third gate insulating layer and has second thickness different from the first thickness in the first direction, and fourth gate electrode on the third gate electrode.

An integrated circuit device is provided that includes a first fin structure and a second fin structure extending from a substrate. The first fin structure is a first composition, and includes rounded corners. The second fin structure is a second composition, different than the first composition. A first interface layer is formed directly on the first fin structure including the rounded corners and a second interface layer directly on the second fin structure. The first interface layer is an oxide of the first composition and the second interface layer is an oxide of the second composition. A gate dielectric layer is formed over the first interface layer and the second interface layer.

In a method of manufacturing a semiconductor device, a dummy gate structure is formed over a substrate. A first insulating layer is formed over the dummy gate structure. The dummy gate structure is removed so as to form a gate space in the first insulating layer. A first conductive layer is formed in the gate space so as to form a reduced gate space. The reduced gate space is filled with a second conductive layer made of a different material from the first conductive layer. The filled first conductive layer and the second conductive layer are recessed so as to form a first gate recess. A third conductive layer is formed over the first conductive layer and the second conductive layer in the first gate recess. After recessing the filled first conductive layer and the second conductive layer, the second conductive layer protrudes from the first conductive layer.

An improvement is achieved in the reliability of a semiconductor device. In a memory cell region, a plurality of fins are provided which are portions of a semiconductor substrate extending in an x-direction along a main surface of the semiconductor substrate and spaced apart from each other in a y-direction orthogonal to the x-direction along the main surface of the semiconductor substrate. Between the fins adjacent to each other in the y-direction, a portion of an upper surface of an isolation region is at a position higher than a surface obtained by connecting a position of the upper surface of the isolation region which is in contact with a side wall of one of the fins to a position of the upper surface of the isolation region which is in contact with a side wall of the other fin. In a cross section along the y-direction, the upper surface of the isolation region has a projecting shape.