Disclosed are a semiconductor structure and a forming method thereof. In one form, a forming method includes: providing a base, including a substrate and a plurality of fins protruding from the substrate, an interlayer dielectric layer formed on the substrate, a gate opening formed in the interlayer dielectric layer, the gate opening spanning the fin and exposing a part of a top and a part of a sidewall of the fin, and a source/drain doped region formed in the fins on two sides of the gate opening, where the substrate includes a first region and a second region adjacent to each other, to respectively form transistors, the gate opening located in either of the first region and the second region extends to the other region and exposes the fin of the other region, and a position of the exposed fin of the other region is used as an interconnect position; forming a gate dielectric layer covering a bottom and a sidewall of the gate opening and the fin in the gate opening conformally; removing the gate dielectric layer on a surface of the fin at the interconnect position, to expose the surface of the fin at the interconnect position; and forming a gate structure in the gate opening after the surface of the fin at the interconnect position is exposed. The present disclosure enlarges a process window for electrical connection.

A semiconductor device includes source and drain regions, a channel region between the source and drain regions, and a gate structure over the channel region. The gate structure includes a gate dielectric over the channel region, a work function metal layer over the gate dielectric and comprising iodine, and a fill metal over the work function metal layer.

A method of fabricating a semiconductor device is described. A substrate is provided. A plurality of fins is formed extending from the substrate, the fins including a first group of active fins arranged in an active region, and including an inactive fin having at least a portion in an inactive region, the active fins separated by first trench regions between adjacent of the active regions, the inactive fin separated from its closest active fin by a second trench region, the second trench region having a greater width than that of a trench region of the first trench regions. A dummy fin is formed on the isolation dielectric in the second trench region, the dummy fin disposed between the first group of active fins and the inactive fin. A dummy gate is formed over the fins. The gate isolation structure is disposed between the dummy fin and the inactive fin and separates regions of the dummy gate.

The present invention relates generally to semiconductors, and more particularly, to a structure and method of minimizing shorting between epitaxial regions in small pitch fin field effect transistors (FinFETs). In an embodiment, a dielectric region may be formed in a middle portion of a gate structure. The gate structure be formed using a gate replacement process, and may cover a middle portion of a first fin group, a middle portion of a second fin group and an intermediate region of the substrate between the first fin group and the second fin group. The dielectric region may be surrounded by the gate structure in the intermediate region. The gate structure and the dielectric region may physically separate epitaxial regions formed on the first fin group and the second fin group from one another.

A method includes forming a first gate dielectric, a second gate dielectric, and a third gate dielectric over a first semiconductor region, a second semiconductor region, and a third semiconductor region, respectively. The method further includes depositing a first lanthanum-containing layer overlapping the first gate dielectric, and depositing a second lanthanum-containing layer overlapping the second gate dielectric. The second lanthanum-containing layer is thinner than the first lanthanum-containing layer. An anneal process is then performed to drive lanthanum in the first lanthanum-containing layer and the second lanthanum-containing layer into the first gate dielectric and the second gate dielectric, respectively. During the anneal process, the third gate dielectric is free from lanthanum-containing layers thereon.

A semiconductor structure has a frontside and a backside. The semiconductor structure includes an isolation structure at the backside; one or more transistors at the frontside, wherein the one or more transistors have source/drain electrodes; two metal plugs through the isolation structure and contacting two of the source/drain electrodes from the backside, wherein the two metal plugs and the isolation structure form sidewalls of a trench; and a dielectric liner on the sidewalls of the trench, wherein the dielectric liner partially or fully surrounds an air gap within the trench.

Backside interconnect structures having reduced critical dimensions for semiconductor devices and methods of forming the same are disclosed. In an embodiment, a device includes a first transistor structure over a front-side of a substrate; a first backside interconnect structure over a backside of the substrate, the first backside interconnect structure including first conductive features having tapered sidewalls with widths that narrow in a direction away from the substrate; a power rail extending through the substrate, the power rail being electrically coupled to the first conductive features; and a first source/drain contact extending from the power rail to a first source/drain region of the first transistor structure.

The present disclosure relates an integrated chip. The integrated chip may include a semiconductor substrate having sidewalls that define a plurality of fins. A dielectric material is arranged between the plurality of fins and a gate structure is disposed over the dielectric material and around the plurality of fins. Epitaxial source/drain regions are disposed along opposing sides of the gate structure and respectively include a plurality of source/drain segments disposed on the plurality of fins and a doped epitaxial material disposed onto and between the plurality of source/drain segments. A first source/drain segment of the plurality of source/drain segments laterally extends in opposing directions to different distances past opposing sides of an underlying first fin of the plurality of fins.

A semiconductor device includes active regions on a substrate, a gate structure intersecting the active regions, a source/drain region on the active regions and at a side surface of the gate structure, a gate spacer between the gate structure and the source/drain region, the gate spacer contacting the side surface of the gate structure, a lower source/drain contact plug connected to the source/drain region, a gate isolation layer on the gate spacer, an upper end of the gate isolation layer being at a higher level than an upper surface of the gate structure and an upper surface of the lower source/drain contact plug, a capping layer covering the gate structure, the lower source/drain contact plug, and the gate isolation layer, and an upper source/drain contact plug connected to the lower source/drain contact plug and extending through the capping layer.

A method of fabricating a semiconductor device includes forming a gate structure, a first edge structure and a second edge structure on a semiconductor strip. The method further includes forming a first source/drain feature between the gate structure and the first edge structure. The method further includes forming a second source/drain feature between the gate structure and the second edge structure, wherein a distance between the gate structure and the first source/drain feature is different from a distance between the gate structure and the second source/drain feature. The method further includes implanting a buried channel in the semiconductor strip, wherein the buried channel is entirely below a top-most surface of the semiconductor strip, a maximum depth of the buried channel is less than a maximum depth of the first source/drain feature, and a dopant concentration of the buried channel is highest under the gate structure.