A method for producing a 3D memory device including: providing a first level including a single crystal layer and control circuits, where the control circuits include a plurality of first transistors; forming at least one second level above the first level; performing a first etch step including etching holes within the second level; performing processing steps to form a plurality of first memory cells within the second level, where each of the first memory cells include one of a plurality of second transistors, where the control circuits include memory peripheral circuits, where at least one first memory cell is at least partially atop a portion of the memory peripheral circuits, and where fabrication processing of the first transistors accounts for a temperature and time associated with processing the second level and the plurality of second transistors by adjusting a process thermal budget of the first level accordingly.

A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where the first transistors each include a single crystal channel; first metal layers interconnecting at least the first transistors; a second metal layer overlaying the first metal layers; and a second level including a second single crystal layer, the second level including second transistors, where the second level overlays the first level, where the second transistors each include at least two side-gates, where the second level is bonded to the first level, and where the bonded includes oxide to oxide bonds.

A method for producing a 3D semiconductor device including: providing a first level including a first single crystal layer; forming peripheral circuitry in and/or on the first level, and includes first single crystal transistors; forming a first metal layer on top of the first level; forming a second metal layer on top of the first metal layer; forming second level disposed on top of the second metal layer; performing a first lithography step; forming a third level on top of the second level; performing a second lithography step; processing steps to form first memory cells within the second level and second memory cells within the third level, where the plurality of first memory cells include at least one second transistor, and the plurality of second memory cells include at least one third transistor; and deposit a gate electrode for second and third transistors simultaneously.

A standard cell includes a plurality of transistors, a set of contacts coupled to the plurality of transistors, at least one input line electrically coupled to the plurality of transistors, an output line electrically coupled to the plurality of transistors, a VDD contacting line electrically coupled to the plurality of transistors and a VSS contacting line electrically coupled to the plurality of transistors. Wherein as a minimum feature size (λ) of the standard cell gradually decreases from 22 nm, an area size of the standard cell in terms of λ.sup.2 is the same or substantially the same.

A semiconductor device, includes a plurality of semiconductor elements, each of the plurality of semiconductor elements including a gate structure extending in a first direction and an active region provided on both sides of the gate structure in a second direction intersecting the first direction; and a plurality of interconnection patterns connected to the plurality of semiconductor elements, wherein the plurality of interconnection patterns include a plurality of upper interconnections provided above the plurality of semiconductor elements in a third direction, a plurality of intermediate interconnections provided between the plurality of semiconductor elements and the plurality of upper interconnections in the third direction, and a routing interconnection adjacent to at least one of the plurality of semiconductor elements in the second direction, wherein the routing interconnection is connected to at least one of the plurality of intermediate interconnections in the first direction or the second direction.

An integrated circuit (IC) device including a fin-type active region on a substrate and a gate line on the fin-type active and having a first uppermost surface at a first vertical level, an insulating spacer covering a sidewall of the gate line and having a second uppermost surface at the first vertical level, and an insulating guide film covering the second uppermost surface of the insulating spacer may be provided. The gate line may include a multilayered conductive film structure that includes a plurality of conductive patterns and have a top surface defined by the conductive patterns, which includes at least first and second conductive patterns including different materials from each other and a unified conductive pattern that is in contact with a top surface of each of the conductive patterns and has a top surface that defines the first uppermost surface.

A 3D semiconductor device, the device comprising: a first level comprising a first single crystal layer, said first level comprising first transistors, wherein each of said first transistors comprises a single crystal channel; first metal layers interconnecting at least said first transistors; a second metal layer overlaying said first metal layers; and a second level comprising a second single crystal layer, said second level comprising second transistors, wherein said second level overlays said first level, wherein at least one of said second transistors comprises a gate all around structure, wherein said second level is directly bonded to said first level, and wherein said bonded comprises direct oxide to oxide bonds.

Integrated circuits including an integrated standard cell structure are provided. In an embodiment, an integrated circuit includes a first transistor gated by a first input and connected to a first power supply rail and an output, a second transistor gated by a second input and connected to the first power supply rail and the output, a floating third transistor and a fourth transistor that are connected to the first power supply rail and a third power supply rail, a fifth transistor gated by the first input and connected to a second power supply rail, a sixth transistor gated by the second input and connected to the second power supply rail, a seventh transistor gated by the second input and connected to the fifth transistor and the output, and an eighth transistor gated by the first input and connected to the sixth transistor and the output.

The present disclosure describes an example method for routing a standard cell with multiple pins. The method can include modifying a dimension of a pin of the standard cell, where the pin is spaced at an increased distance from a boundary of the standard cell than an original position of the pin. The method also includes routing an interconnect from the pin to a via placed on a pin track located between the pin and the boundary and inserting a keep out area between the interconnect and a pin from an adjacent standard cell. The method further includes verifying that the keep out area separates the interconnect from the pin from the adjacent standard cell by at least a predetermined distance.

Placement methods described in this disclosure provide placement and routing rules where a system implementing the automatic placement and routing (APR) method arranges standard cell structures in a vertical direction that is perpendicular to the fins but parallel to the cell height. Layout methods described in this disclosure also improve device density and further reduce cell height by incorporating vertical power supply lines into standard cell structures. Pin connections can be used to electrically connect the power supply lines to standard cell structures, thus improving device density and performance. The APR process is also configured to rotate standard cells to optimize device layout.