Patent classifications
H01L27/14612
SOLID-STATE IMAGE SENSOR AND IMAGING SYSTEM
A solid-state image sensor includes a first semiconductor, and a second semiconductor having a composition different from that of the first composition and electrically connected to the first semiconductor. The first semiconductor includes a photodiode that converts light incident on the photodiode into charge carriers, first carrier storages that store the charge carriers, and a transfer gate that controls transfer the charge carriers to a selected one of the first carrier storages. The second semiconductor includes second carrier storages and a potential detection node. The second carrier storages each store charge carriers based on the charge carriers stored in a corresponding one of the first carrier storages. The potential detection node detects the electric potential of each of the second carrier storages. The solid-state image sensor further includes a reset transistor that resets the electric potential of each of the first carrier storages to a predetermined electric potential.
MULTILEVEL SEMICONDUCTOR DEVICE AND STRUCTURE WITH IMAGE SENSORS AND WAFER BONDING
An integrated device, the device including: a first level including a first mono-crystal layer, the first mono-crystal layer including a plurality of single crystal transistors; an overlying oxide disposed on top of the first level; a second level including a second mono-crystal layer, the second level overlaying the oxide, where the second mono-crystal layer includes a plurality of semiconductor devices; a third level overlaying the second level, where the third level includes a plurality of image sensors, where the first level includes a plurality of landing pads, where the second level is bonded to the first level, where the bonded includes an oxide to oxide bond; and an isolation layer disposed between the second mono-crystal layer and the third level.
IMAGE SENSOR WITH CONTROLLED SPAD AVALANCHE
There is provided an image sensor employing an avalanche diode. The image sensor includes a plurality of pixel circuits arranged in a matrix, a plurality of pulling circuits and a global current source circuit. Each of the plurality of pixel circuits includes a single photon avalanche diode (SPAD) and a floating diffusion. Each of the plurality of pulling circuits is arranged corresponding to one pixel circuit column. The global current source circuit is used to form a current mirror with each of the plurality of pulling circuits. The floating diffusion is used to record a voltage of one photon event detected by the SPAD in an exposure period.
SOLID-STATE IMAGING DEVICE
A solid-state imaging device includes: pixels arranged in a matrix; a vertical signal line provided for each column, conveying a pixel signal; a power line provided for each column, proving a power supply voltage; and a feedback signal line provided for each column, conveying a signal from a peripheral circuit to a pixel, in which each of the pixels includes: an N-type diffusion layer; a photoelectric conversion element above the N-type diffusion layer; and a charge accumulation node between the N-type diffusion layer and the photoelectric conversion element, accumulating signal charge generated in the photoelectric conversion element, the feedback signal line, a metal line which is a part of the charge accumulation node, the vertical signal line, and the power line are disposed in a second interconnect layer, and the vertical signal line and the power line are disposed between the feedback signal line and the metal line.
IMAGE SENSOR WITH PIXEL STRUCTURE INCLUDING FLOATING DIFFUSION AREA SHARED BY PLURALITY OF PHOTOELECTRIC CONVERSION ELEMENTS AND A SIGNAL READOUT MODE
An image sensor is provided. The image sensor includes: a pixel array including a plurality of pixels arranged along rows and columns; and a row driver which drives the plurality of pixels for each of the rows, wherein each of the plurality of pixels includes a plurality of sub-pixels, each of the plurality of sub-pixels includes a plurality of photoelectric conversion elements sharing a floating diffusion area with each other, and a micro lens disposed to overlap the plurality of photoelectric conversion elements, a readout area is defined on the pixel array in accordance with a preset readout mode, and the row driver generates a drive signal for reading out signals provided from a photoelectric conversion element included in the readout area from among the plurality of photoelectric conversion elements, and provides the drive signal to the pixel array.
TRANSISTOR STRUCTURES
Transistor structures for a transistor may include a first source-drain region, a second source-drain region, and a channel region between the first and second source-drain regions overlapped by a gate structure. Transistor structures may be formed in a well of a first doping type. Isolation structures having the first doping type may be formed within the well. A lightly doped implant region of a second doping type for each of the source-drain regions may be formed within the well and separated from the isolation structures. A heavily doped surface implant region of the first doping type may extend across the surface of the well and cover the lightly doped implant region of each source-drain region. The surface implant region may be formed by patterning or by a blanket implantation process across the transistor structures.
Solid-state imaging device with layered microlenses and method for manufacturing same
A solid-state imaging device includes: a first lens layer; and a second lens layer, wherein the second lens layer is formed at least at a periphery of each first microlens formed based on the first lens layer, and the second lens layer present at a central portion of each of the first microlenses is thinner than the second lens layer present at the periphery of the first microlens or no second lens layer is present at the central portion of each of the first microlenses.
Semiconductor device, display device including the semiconductor device, display module including the display device, and electronic device including the semiconductor device, the display device, and the display module
To provide a semiconductor device including a planar transistor having an oxide semiconductor and a capacitor. In a semiconductor device, a transistor includes an oxide semiconductor film, a gate insulating film over the oxide semiconductor film, a gate electrode over the gate insulating film, a second insulating film over the gate electrode, a third insulating film over the second insulating film, and a source and a drain electrodes over the third insulating film; the source and the drain electrodes are electrically connected to the oxide semiconductor film; a capacitor includes a first and a second conductive films and the second insulating film; the first conductive film and the gate electrode are provided over the same surface; the second conductive film and the source and the drain electrodes are provided over the same surface; and the second insulting film is provided between the first and the second conductive films.
Image sensor and method of manufacturing same
An image sensor having a shield including, for example, a metal, is above an electrical charge storage element in a pixel region to block light incident toward the electrical charge storage element, thereby making it possible to reduce or prevent reading a charge value including leakage charge introduced to the electrical charge storage element, and thus adversely affecting an image result.
IMAGE SENSOR USING TRANSFER GATE SIGNAL HAVING THREE VOLTAGE LEVELS, AND METHOD OF OPERATING THE SAME
A method of operating an image sensor includes accumulating first charges through a photo diode, applying a first transfer gate signal having a first voltage level to a transfer transistor, performing, through a reset transistor, a first reset operation on a floating diffusion node connected with the reset transistor and the transfer transistor, changing the first voltage level of the first transfer gate signal to a second voltage level higher than the first voltage level, during the first reset operation, changing the second voltage level of the first transfer gate signal to a third voltage level higher than the second voltage level, and changing the third voltage level of the first transfer gate signal to the second voltage level.