An imaging device may include single-photon avalanche diodes (SPADs). To improve the sensitivity and signal-to-noise ratio of the SPADs, light scattering structures may be formed in the semiconductor substrate to increase the path length of incident light through the semiconductor substrate. To mitigate crosstalk, an isolation structure may be formed in a ring around the SPAD. The isolation structure may be a hybrid isolation structure with both a metal filler that absorbs light and a low-index filler that reflects light. The isolation structure may be formed as a single trench or may include a backside deep trench isolation portion and a front side deep trench isolation portion. The isolation structure may also include a color filtering material.

An imaging element is disclosed that includes: a semiconductor substrate; a multilayer wiring layer; a plurality of structures; and a light reflecting layer. The semiconductor substrate has a first surface as a light incidence surface and a second surface opposite to the first surface. A light receiving section of the semiconductor substrate generates electric charge through photoelectric conversion. The multilayer wiring layer has a plurality of wiring layers and is on the second surface side of the semiconductor substrate. The plurality of structures is in the multilayer wiring layer. The light reflecting layer is in the multilayer wiring layer, and forms a reflective region or a non-reflective region in a region with the interlayer insulating layer interposed in between. The region has none of the structures formed therein. The reflective region and the non-reflective region are substantially symmetrical with respect to the optical center of the pixel.

The present technology relates to an imaging element and an electronic device capable of preventing light from leaking into an adjacent pixel. A semiconductor layer in which a first pixel in which a read pixel signal is used to generate an image, and a second pixel in which the read pixel signal is not used to generate an image are arranged, and a wiring layer stacked on the semiconductor layer are provided, and a structure of the first pixel and a structure of the second pixel are different. A first inter-pixel separation portion that separates the semiconductor layer of the adjacent first pixels, and a second inter-pixel separation portion that separates the semiconductor layer of the adjacent second pixels are further provided, and the first inter-pixel separation portion and the second inter-pixel separation portion are provided with different structures. The present technology can be applied to an imaging element in which dummy pixels are arranged.

An imaging device includes a counter electrode, a photoelectric conversion layer that converts light into a signal charge, a plurality of sets of electrodes each of which collects the signal charge, each of the plurality of sets including a first electrode included in a high-sensitivity pixel and a second electrode included in a low-sensitivity pixel, and an auxiliary electrode which is located, as seen in plan view, between the first electrode and the second electrode in each of the plurality of sets and which is commonly included in the high-sensitivity pixel and the low-sensitivity pixel. The distance between the first electrode and the auxiliary electrode is different from the distance between the second electrode and the auxiliary electrode.

A semiconductor apparatus includes a stack of a first chip having a plurality of pixel circuits arranged in a matrix form and a second chip having a plurality of electric circuit arranged in a matrix form. A wiring path between a semiconductor element configuring the pixel circuit and a semiconductor element configuring the electric circuit or a positional relationship between a semiconductor element configuring the pixel circuit and a semiconductor element configuring the electric circuit is differentiated among the electric circuits.

The present technology relates to a solid-state imaging device and electronic equipment to suppress degradation of Dark characteristics. A photoelectric converting unit configured to perform photoelectric conversion, and a PN junction region including a P-type region and an N-type region on a side of a light incident surface of the photoelectric converting unit are included. Further, on a vertical cross-section, the PN junction region is formed at three sides including a side of the light incident surface among four sides enclosing the photoelectric converting unit. Further, a trench which penetrates through a semiconductor substrate in a depth direction and which is formed between the photoelectric converting units each formed at adjacent pixels is included, and the PN junction region is also provided on a side wall of the trench. The present technology can be applied, for example, to a backside irradiation type CMOS image sensor.

The disclosure provides an image sensor integrated chip and a method for forming the same. The image sensor integrated chip includes a substrate, an isolation structure, an image sensing element, a gate structure, a first dielectric layer, and a reflective layer. The substrate includes a pixel region. The isolation structure is disposed in the substrate and is configured at opposite sides of the pixel region. The image sensing element is disposed in the pixel region of the substrate. The gate structure is disposed on the pixel region of the substrate. The first dielectric layer is disposed above the pixel region of the substrate and covers sidewalls and a portion of a top surface of the gate structure. The reflective layer is disposed on the first dielectric layer. The reflective layer overlaps with the image sensing element and the portion of the top surface of the gate structure in a first direction perpendicular to a surface of the substrate.

Photoelectric conversion apparatus including semiconductor layer includes pixel array region and peripheral region. The semiconductor layer has first and second faces. Each pixel includes first semiconductor region of first conductivity type arranged on the first face side and second semiconductor region of second conductivity type arranged on the second face side, and predetermined voltage causing avalanche multiplication operation is supplied between the first semiconductor region and the second semiconductor region. The peripheral region includes third semiconductor region of the first conductivity type arranged on the first face side, fourth semiconductor region of the second conductivity type arranged apart from the third semiconductor region, and fifth semiconductor region of the first conductivity type arranged, close to the third semiconductor region, between the third semiconductor region and the fourth semiconductor region.

A backside-illuminated image sensor includes arrayed photodiodes separated by isolation structures, and interlayer dielectric between first layer of metal interconnect and substrate. The image sensor has barrier metal walls in the interlayer dielectric between isolation structures and first layer interconnect, the barrier metal walls aligned with the isolation structures and disposed between the isolation structures and first layer interconnect. The barrier metal wall deflects light passing through photodiodes of the sensor that would otherwise be reflected by interconnect into different photodiodes. The sensor is formed by providing a partially fabricated semiconductor substrate with photodiodes and source-drain regions formed; forming gate electrodes on a frontside surface of the semiconductor substrate, depositing an etch-stop layer over the gate electrodes; depositing interlayer dielectric on the etch-stop layer; forming trenches extending to the etch-stop layer through the interlayer dielectric, the trenches being between photodiodes; and filling trenches with metal to form barrier metal walls.

A photoelectric conversion apparatus includes a first semiconductor layer having a photoelectric conversion element, a second semiconductor layer including circuitry for processing a signal based on a charge obtained by the photoelectric conversion element, a first wiring structure electrically connected to the first semiconductor layer, a second wiring structure electrically connected to the second semiconductor layer, and a coupling part that couples the first wiring structure to the second wiring structure. In a plan view, the apparatus includes a pixel region having the photoelectric conversion element, and a peripheral region located between the pixel region and an outer edge of the photoelectric conversion apparatus. The first wiring structure includes, in the peripheral region, a first conductive part having a mesh-shaped part. The first conductive part is connected to a pad facing outside the photoelectric conversion apparatus.