Patent classifications
H01L27/14812
INTEGRATED DEVICE FOR TEMPORAL BINNING OF RECEIVED PHOTONS
An integrated circuit includes a photodetection region configured to receive incident photons. The photodetection region is configured to produce a plurality of charge carriers in response to the incident photons. The integrated circuit also includes at least one charge carrier storage region. The integrated circuit also includes a charge carrier segregation structure configured to selectively direct charge carriers of the plurality of charge carriers into the at least one charge carrier storage region based upon times at which the charge carriers are produced.
Image sensing device
The image sensing device includes a pixel array including a plurality of unit pixels is arranged in rows and columns. Each of the plurality of unit pixels includes a photoelectric conversion element to generate charge carriers by converting light incident upon the photoelectric conversion element, a plurality of floating diffusion regions spaced apart from the photoelectric conversion element to hold the charge carriers, a plurality of circulation gates located at sides of the photoelectric conversion element in each of a first direction and a second direction perpendicular to the first direction, configured to create an electric field in different regions of the photoelectric conversion element based on circulation control signals, and configured to induce movement of the charge carriers, and a plurality of transfer gates located between the circulation gates, and configured to transfer the charge carriers generated by the photoelectric conversion element to a corresponding floating diffusion region.
CIRCUIT FOR REDUCED CHARGE-INJECTION ERRORS
A switch circuit for use in a single-ended switched-capacitor circuit for front-end circuitry of a sensor device is disclosed. The switch circuit comprises a first transistor and a second transistor having a same channel-type as the first transistor. A first node is connected to a source of the first transistor and a drain of the second transistor and a second node is connected to a drain of the first transistor and a source of the second transistor. Also disclosed is a sampling circuit comprising the switch circuit and a sampling capacitor, wherein the switch circuit is configurable to electrically couple the sampling capacitor to an integrator circuit or to a voltage reference. An integrated circuit device and a light to frequency converter or light sensor comprising the switch circuit is also disclosed.
Image processing method and apparatus
An image processing method and apparatus. The method includes: obtaining a source image; determining spot superposition positions according to pixel values of the source image, where values of pixels of the source image that are located in the spot superposition positions are greater than a preset first threshold; and blurring the source image, and performing, in the spot superposition positions of a source image, image fusion on the source image and spot images to obtain a processed image, where the spot superposition positions and the spot images fused with in the spot superposition positions are in a one-to-one correspondence.
IMAGE SENSOR
Disclosed is an image sensor including a substrate having a first surface and a second surface opposite to each other, a first photoelectric conversion region and a second photoelectric conversion region in the substrate, a through electrode between the first and second photoelectric conversion regions, an insulation structure on the second surface of the substrate, a first color filter and a second color filter respectively provided on the first and second photoelectric conversion regions, and a photoelectric conversion layer on the insulation structure and electrically connected to the through electrode. The through electrode include a first end adjacent to the first surface and a second end adjacent to the second surface. The first end has a non-planar shape.
Image sensor
Provided is an image sensor including a semiconductor substrate having a first surface and a second surface opposite each other, an organic photoelectric conversion device on the first surface of the semiconductor substrate, a through electrode structure connected to the organic photoelectric conversion device, and a pixel separation structure extending from the first surface toward the second surface of the semiconductor substrate. The semiconductor substrate may include a photoelectric conversion region in the semiconductor substrate. The pixel separation structure may surround the photoelectric conversion region when viewed in plan. The pixel separation structure may include a separation conductive pattern and a first sidewall dielectric pattern. The first sidewall dielectric pattern may continuously extend from between the separation conductive pattern and the semiconductor substrate to between the semiconductor substrate and a sidewall of the through electrode structure. A portion of the pixel separation structure penetrated by the through electrode structure.
Integrated device for temporal binning of received photons
An integrated circuit includes a photodetection region configured to receive incident photons. The photodetection region is configured to produce a plurality of charge carriers in response to the incident photons. The integrated circuit also includes at least one charge carrier storage region. The integrated circuit also includes a charge carrier segregation structure configured to selectively direct charge carriers of the plurality of charge carriers into the at least one charge carrier storage region based upon times at which the charge carriers are produced.
Integrated photodetector with direct binning pixel
An integrated circuit includes a photodetection region configured to receive incident photons. The photodetection region is configured to produce a plurality of charge carriers in response to the incident photons. The integrated circuit includes at least one charge carrier storage region. The integrated circuit also includes a charge carrier segregation structure configured to selectively direct charge carriers of the plurality of charge carriers directly into the at least one charge carrier storage region based upon times at which the charge carriers are produced.
PIXEL-ARRAY SUBSTRATE AND ASSOCIATED METHOD
A pixel-array substrate includes a floating diffusion region and a first photodiode formed in a semiconductor substrate. A top surface of the semiconductor substrate defines a trench 1A and a trench 1B each (i) extending into the semiconductor substrate away from a planar region of the top surface between the trench 1A and the trench 1B and (ii) having a respective distal end, with respect to the floating diffusion region, located between the floating diffusion region and the first photodiode. In a horizontal plane parallel to the top surface and along an inter-trench direction between the trench 1A and the trench 1B, a first spatial separation between the trench 1A and the trench 1B increases with increasing distance from the floating diffusion region.
IMAGE SENSING DEVICE
An image sensing device includes a substrate including a back side structured to receive incident light and a front side opposite to the back side; imaging pixels to receive the incident light from the back side and each imaging pixel structured to produce photocharge in response to received incident light; a plurality of conductive contact structures configured to generate a potential gradient in the substrate and to capture photocharges that are generated in response to the incident light and move by the potential gradient; and a well region disposed between the plurality of conductive contact structures.