Patent classifications
H01L29/068
METHODS AND DEVICES FOR FABRICATING AND ASSEMBLING PRINTABLE SEMICONDUCTOR ELEMENTS
The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials. The present invention also provides stretchable semiconductor structures and stretchable electronic devices capable of good performance in stretched configurations.
SEMICONDUCTOR DEVICE
A semiconductor device includes a drain, a source, a gate electrode, and a nanowire between the source and drain. The nanowire has a first section with a first thickness and a second section with a second thickness greater than the first thickness. The second section is between the first section and at least one of the source or drain. The first nanowire includes a channel when a voltage is applied to the gate electrode.
Method of manufacturing a semiconductor device and a semiconductor device
A method of manufacturing a semiconductor device includes forming a first semiconductor layer having a first composition over a semiconductor substrate, and forming a second semiconductor layer having a second composition over the first semiconductor layer. Another first semiconductor layer having the first composition is formed over the second semiconductor layer. A third semiconductor layer having a third composition is formed over the another first semiconductor layer. The first semiconductor layers, second semiconductor layer, and third semiconductor layer are patterned to form a fin structure. A portion of the third semiconductor layer is removed thereby forming a nanowire comprising the second semiconductor layer, and a conductive material is formed surrounding the nanowire. The first semiconductor layers, second semiconductor layer, and third semiconductor layer include different materials.
FLOATING GATE SEMICONDUCTOR NANOSTRUCTURE-BASED BIOSENSOR AND METHOD FOR MANUFACTURING SAME
In a floating gate semiconductor nanostructure biosensor and a method for manufacturing the biosensor, the nanostructure biosensor includes a substrate, an insulating layer, a nanostructure, a source electrode and a drain electrode, a floating gate and a biological sensing material. The insulating layer is formed on the substrate. The nanostructure is protruded from the insulating layer. The source electrode and the drain electrode are formed on the insulating layer and dispose the nanostructure therebetween. The floating gate has a metal pattern or a polysilicon pattern, and extends with contacting the nanostructure. The biological sensing material has a first end combined with an immobile molecule on the floating gate, and a second end combined with a bio molecule.
REINFORCED THIN-FILM DEVICE
A reinforced thin-film device is disclosed. The reinforced thin-film device comprising: a substrate having a top surface for supporting an epilayer; a mask layer patterned with a plurality of nanosize cavities disposed on said substrate to form a needle pad; a thin-film of, relative to the substrate, lattice-mismatched semiconductor disposed on said mask layer, wherein said thin-film comprises a plurality of in parallel spaced semiconductor needles of said lattice-mismatched semiconductor embedded in said thin-film, wherein said plurality of semiconductor needles are vertically disposed in the axial direction towards said substrate in said plurality of nanosize cavities of said mask layer; a, relative to the substrate, lattice-mismatched semiconductor epilayer provided on said thin-film and supported thereby; and a FinFET transistor arranged on the lattice-mismatched semiconductor epilayer. The FinFET transistor comprising: a fin semiconductor structure comprising an elongate protruding core portion, the fin semiconductor structure being arranged on the lattice-mismatched semiconductor epilayer, a first and a second nanostructured electrode radially enclosing respectively a source end and a drain end of the protruding core portion, and a nanostructured gate electrode radially enclosing a central portion of the protruding core portion, the central portion being a portion of the protruding core portion between the source end and the drain end.
GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING DEPOPULATED CHANNEL STRUCTURES USING MULTIPLE BOTTOM-UP OXIDATION APPROACHES
Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using multiple bottom-up oxidation approaches, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires. All nanowires of the vertical arrangement of nanowires are oxide nanowires. A gate stack is over the vertical arrangement of nanowires, around each of the oxide nanowires. The gate stack includes a conductive gate electrode.
Floating gate semiconductor nanostructure-based biosensor and method for manufacturing same
In a floating gate semiconductor nanostructure biosensor and a method for manufacturing the biosensor, the nanostructure biosensor includes a substrate, an insulating layer, a nanostructure, a source electrode and a drain electrode, a floating gate and a biological sensing material. The insulating layer is formed on the substrate. The nanostructure is protruded from the insulating layer. The source electrode and the drain electrode are formed on the insulating layer and dispose the nanostructure therebetween. The floating gate has a metal pattern or a polysilicon pattern, and extends with contacting the nanostructure. The biological sensing material has a first end combined with an immobile molecule on the floating gate, and a second end combined with a bio molecule.
A METHOD FOR FABRICATING AN ASYMMETRIC VERTICAL NANOWIRE MOSFET AND AN ASYMMETRIC VERTICAL NANOWIRE MOSFET
There is provided a method for fabricating an asymmetric vertical nanowire MOSFET on a semiconductor substrate comprising at least one vertical nanowire, comprising a core portion and a shell portion circumscribing the core portion. The method comprises depositing a protection layer on the semiconductor substrate, forming a top contact around a remaining portion of the vertical nanowire not covered by the protection layer, removing the protection layer, depositing a spacer layer on the semiconductor substrate, removing a shell portion of the intermediate portion of the bottom portion of the vertical nanowire, trimming a shell portion of the upper portion of the bottom portion of the vertical nanowire, depositing a metal gate on the spacer layer, and forming a lower and an upper source drain portions.
COMPLEMENTARY SWITCH ELEMENT
This complementary switch element includes: a first TFET having a first conductive channel; and a second TFET having a second conductive channel. Each of the first TFET and the second TFET includes: a group IV semiconductor substrate doped in a first conductive type; a nanowire which is formed of a group III-V compound semiconductor and is disposed on the group IV semiconductor substrate; a first electrode connected to the group IV semiconductor substrate; a second electrode connected to the nanowire; and a gate electrode. The nanowire includes a first area connected to the group IV semiconductor substrate and a second area doped in a second conductive type. In the first TFET, the second electrode is a source electrode, and the first electrode is a drain electrode. In the second TFET, the first electrode is a source electrode, and the second electrode is a drain electrode.
Semiconductor device and radio receiver using the same
A semiconductor device includes: a first conductivity type semiconductor of a nanostructure; a first electrode that is in ohmic junction with an end part of the first conductivity type semiconductor; a second electrode that is coupled to the first electrode and is provided over a side surface of the first conductivity type semiconductor; and a depletion constituent that controls expansion of a depletion layer inside the nanostructure, wherein the depletion layer is expanded inside the first conductivity type semiconductor by the depletion constituent in a direction intersecting a movement direction of a carrier.