Patent classifications
H01L29/154
Methods of forming substrate structures and semiconductor components
In an embodiment, a method includes forming an intentionally doped superlattice laminate on a support substrate, forming a Group III nitride-based device having a heterojunction on the superlattice laminate layer, and forming a charge blocking layer between the heterojunction and the superlattice laminate.
NITRIDE SEMICONDUCTOR ELEMENT AND NITRIDE SEMICONDUCTOR PACKAGE
A nitride semiconductor element capable of accommodating GaN electron transfer layers of a wide range of thickness, so as to allow greater freedom of device design, and a nitride semiconductor element package with excellent voltage tolerance performance and reliability. On a substrate, a buffer layer including an AlN layer, a first AlGaN layer and a second AlGaN layer is formed. On the buffer layer, an element action layer including a GaN electron transfer layer and an AlGaN electron supply layer is formed. Thus, an HEMT element is constituted.
Semiconductor device including a superlattice and replacement metal gate structure and related methods
A semiconductor device may include a substrate having a channel recess therein, a plurality of spaced apart shallow trench isolation (STI) regions in the substrate, and source and drain regions spaced apart in the substrate and between a pair of the STI regions. A superlattice channel may be in the channel recess of the substrate and extend between the source and drain regions, with the superlattice channel including a plurality of stacked group of layers, and each group of layers of the superlattice channel including stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A replacement gate may be over the superlattice channel.
Nitride semiconductor element and nitride semiconductor package
A nitride semiconductor element capable of accommodating GaN electron transfer layers of a wide range of thickness, so as to allow greater freedom of device design, and a nitride semiconductor element package with excellent voltage tolerance performance and reliability. On a substrate, a buffer layer including an AlN layer, a first AlGaN layer and a second AlGaN layer is formed. On the buffer layer, an element action layer including a GaN electron transfer layer and an AlGaN electron supply layer is formed. Thus, an HEMT element is constituted.
NITRIDE SEMICONDUCTOR ELEMENT AND NITRIDE SEMICONDUCTOR PACKAGE
A nitride semiconductor element capable of accommodating GaN electron transfer layers of a wide range of thickness, so as to allow greater freedom of device design, and a nitride semiconductor element package with excellent voltage tolerance performance and reliability. On a substrate, a buffer layer including an AlN layer, a first AlGaN layer and a second AlGaN layer is formed. On the buffer layer, an element action layer including a GaN electron transfer layer and an AlGaN electron supply layer is formed. Thus, an HEMT element is constituted.
METHODS FOR MAKING SEMICONDUCTOR DEVICES INCLUDING LOCALIZED SEMICONDUCTOR-ON-INSULATOR (SOI) REGIONS
A method for making a semiconductor device may include forming buried spaced-apart insulator regions in a semiconductor substrate, and forming a monocrystalline semiconductor layer on the semiconductor substrate defining respective localized semiconductor on insulator (SOI) regions above the buried insulator regions, and respective localized bulk semiconductor regions laterally between adjacent SOI regions. The method may also include forming a superlattice in the monocrystalline semiconductor layer. The superlattice may include stacked groups of layers, with each group of layers including stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming semiconductor devices in the monocrystalline layer, with some of the semiconductor devices in the localized SOI regions, and some other semiconductor devices in the localized bulk semiconductor regions.
SEMICONDUCTOR DEVICES INCLUDING LOCALIZED SEMICONDUCTOR-ON-INSULATOR (SOI) REGIONS
A semiconductor device may include a semiconductor substrate, buried spaced-apart insulator regions in the substrate, and a monocrystalline semiconductor layer on the semiconductor substrate defining respective localized semiconductor on insulator (SOI) regions above the buried insulator regions, and respective localized bulk semiconductor regions laterally between adjacent SOI regions. The semiconductor device may also include a superlattice in the monocrystalline semiconductor layer. The superlattice may include stacked groups of layers, with each group of layers including stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include semiconductor devices in the monocrystalline layer, with at least some of the semiconductor devices in the localized SOI regions, and at least some other semiconductor devices in the localized bulk semiconductor regions.
Nitride semiconductor element and nitride semiconductor package
A nitride semiconductor element capable of accommodating GaN electron transfer layers of a wide range of thickness, so as to allow greater freedom of device design, and a nitride semiconductor element package with excellent voltage tolerance performance and reliability. On a substrate, a buffer layer including an AlN layer, a first AlGaN layer and a second AlGaN layer is formed. On the buffer layer, an element action layer including a GaN electron transfer layer and an AlGaN electron supply layer is formed. Thus, an HEMT element is constituted.
Methods of Forming Substrate Structures and Semiconductor Components
In an embodiment, a method includes forming an intentionally doped superlattice laminate on a support substrate, forming a Group III nitride-based device having a heterojunction on the superlattice laminate layer, and forming a charge blocking layer between the heterojunction and the superlattice laminate.