A field-effect transistor (FET) includes a fin, an insulator region, and at least one gate. The fin has a doped first region, a doped second region, and an interior region between the first region and the second region. The interior region is undoped or more lightly doped than the first and second regions. The interior region of the fin is formed as a superlattice of layers of first and second materials alternating vertically. The insulator layer extends around the interior region. The gate is formed on at least a portion of the insulator region. The insulator layer and the gate are configured to generate an inhomogeneous electrostatic potential within the interior region, the inhomogeneous electrostatic potential cooperating with physical properties of the superlattice to cause scattering of charge carriers sufficient to change a quantum property of such charge carriers to change the ability of the charge carriers to move between the first and second materials.

A GaN-based power electronic device and a method for manufacturing the same is provided. The GaN-based power electronic device comprising a substrate and an epitaxial layer over the substrate. The epitaxial layer comprises a GaN-based heterostructure layer, a superlattice structure layer and a P-type cap layer. The superlattice structure layer is provided over the heterostructure layer, and the P-type cap layer is provided over the superlattice structure layer. By using this electronic device, gate voltage swing and safe gate voltage range of the GaN-based power electronic device manufactured on the basis of the P-type cap layer technique may be further extended, and dynamic characteristics of the device may be improved. Therefore, application process for the GaN-based power electronic device that is based on the P-type cap layer technique will be promoted.

Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a germanium fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), a doping layer (e.g., delta/modulation doped), and an undoped germanium quantum well layer. An undoped germanium fin structure is formed in the quantum well structure, and a top barrier layer deposited over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.

A high electron mobility transistor (HEMT) device includes at least an AlN nucleation layer, a superlattice composite layer, a GaN electron transport layer, and an AlGaN barrier layer. The superlattice composite layer is disposed on the AlN nucleation layer, and the superlattice composite layer includes a plurality of AlN films and a plurality of GaN films stacked alternately to reduce device stress. The GaN electron transport layer is disposed on the superlattice composite layer, and the AlGaN barrier layer is disposed on the GaN electron transport layer.

An ohmic contact to a semiconductor layer including a heterostructure barrier layer and a metal layer adjacent to the heterostructure barrier layer is provided. The heterostructure barrier layer can form a two dimensional free carrier gas for the contact at a heterointerface of the heterostructure barrier layer and the semiconductor layer. The metal layer is configured to form a contact with the two dimensional free carrier gas.

An integrated circuit die has a layer of first semiconductor material comprising a Group III element and nitrogen and having a first bandgap. A first transistor structure on a first region of the die has: a quantum well (QW) structure that includes at least a portion of the first semiconductor material and a second semiconductor material having a second bandgap smaller than the first bandgap, a first source and a first drain in contact with the QW structure, and a gate structure in contact with the QW structure between the first source and the first drain. A second transistor structure on a second region of the die has a second source and a second drain in contact with a semiconductor body, and a second gate structure in contact with the semiconductor body between the second source and the second drain. The semiconductor body comprises a Group III element and nitrogen.

A crystalline base substrate including a first semiconductor material and having a main surface is provided. The base substrate is processed so as to damage a lattice structure of the base substrate in a first region that extends to the main surface without damaging a lattice structure of the base substrate in second regions that are adjacent to the first region. A first semiconductor layer of a second semiconductor material is formed on a portion of the main surface that includes the first and second regions. A third region of the first semiconductor layer covers the first region of the base substrate, and a fourth region of the first semiconductor layer covers the second region of the base substrate. The third region has a crystalline structure that is disorganized relative to a crystalline structure of the fourth region. The first and second semiconductor materials have different coefficients of thermal expansion.

A hybrid transistor circuit is disclosed for use in III-Nitride (III-N) semiconductor devices, comprising a Silicon (Si)-based Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), a Group III-Nitride (III-N)-based Field-Effect Transistor (FET), and a driver unit. A source terminal of the III-N-based FET is connected to a drain terminal of the Si-based MOSFET. The driver unit has at least one input terminal, and two output terminals connected to the gate terminals of the transistors respectively. The hybrid transistor circuit is turned on through the driver unit by switching on the Silicon-based MOSFET first before switching on the III-N-based FET, and is turned off through the driver unit by switching off the III-N-based FET before switching off the Silicon-based MOSFET. Also disclosed are integrated circuit packages and semiconductor structures for forming such hybrid transistor circuits. The resulting hybrid circuit provides power-efficient and robust use of III-Nitride semiconductor devices.

A device includes insulation regions over portions of a semiconductor substrate, and a III-V compound semiconductor region over top surfaces of the insulation regions, wherein the III-V compound semiconductor region overlaps a region between opposite sidewalls of the insulation regions. The III-V compound semiconductor region includes a first and a second III-V compound semiconductor layer formed of a first III-V compound semiconductor material having a first band gap, and a third III-V compound semiconductor layer formed of a second III-V compound semiconductor material between the first and the second III-V compound semiconductor layers. The second III-V compound semiconductor material has a second band gap lower than the first band gap. A gate dielectric is formed on a sidewall and a top surface of the III-V compound semiconductor region. A gate electrode is formed over the gate dielectric.

According to one embodiment, a memory includes a resistance change layer includes a first chalcogenide layer, and a second chalcogenide layer having a composition different from that of the first chalcogenide layer which are stacked alternately, and the resistance change layer having a superlattice structure, and a semiconductor layer of a first conductivity type provided on a one of main surfaces of the resistance change layer.