A manufacturing method for an array substrate is disclosed. The method includes: forming a gate electrode on a substrate; depositing a gate insulation layer, a semiconductor layer, a source-drain metal layer and a passivation layer on the gate electrode and the substrate, and through a mask process to perform a patterning process to the semiconductor layer, the source-drain metal layer and the passivation layer in order to form a semiconductor pattern, a source-drain pattern and a contact hole pattern; and forming an ITO pixel electrode on the passivation layer and the contact hole pattern. An array substrate is also disclosed. The present invention adopts one mask process to form the semiconductor pattern, the source-drain pattern and the contact hole pattern such that the process of the array substrate is reduced to three masks in order to reduce the manufacturing cost, reduce the operation time and increase the production efficiency.

An HEMT includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer is different from the composition of the second III-V compound layer. A third III-V compound layer is disposed on the second III-V compound layer. The first III-V compound layer and the third III-V compound layer are composed of the same group III-V elements. The third III-V compound layer includes a body and numerous finger parts. Each of the finger parts is connected to the body. All finger parts are parallel to each other and do not contact each other. A source electrode, a drain electrode and a gate electrode are disposed on the first III-V compound layer.

A tunable homojunction field effect device-based artificial synapse circuit includes a first tunable homojunction field effect device M1, a second tunable homojunction field effect device M2, a third tunable homojunction field effect device M3, and a capacitor C; the tunable homojunction field effect device can exhibit the electrical properties of NN junction, PP junction, PN junction, and NP junction under the control of gate voltage; in the circuit, whether the device M2 and the device M3 are turned on rely on the combined action of presynaptic pulse and postsynaptic pulse; compared with the circuit structure of a traditional CMOS circuit scheme which exhibits neural synaptic functions of spike-time-dependent plasticity and continuously adjustable pulse-to-synaptic weight, the circuit in the present solution requires a greatly reduced number of devices and shows the feature of reconfigurable function, exhibiting a great advantage in constructing low-power, high-density integrated bionic chips for future neuromorphic applications.

The present disclosure provides a ferroelectric field-effect transistor comprising: a substrate comprising a source region, a channel, and a drain region; a ferroelectric material arranged on a first portion of the channel and a portion of the drain region; a program gate arranged on the ferroelectric material and being at least coextensive with the first portion of the channel; a gate dielectric arranged on a portion of the source region and a second portion of the channel; and a select gate arranged on the gate dielectric and being at least coextensive with said portion of the source region and the second portion of the channel; wherein a well of the substrate extending under the whole channel has a uniform doping level.

A semiconductor device structure, along with methods of forming such, are described. The structure includes a plurality of semiconductor layers and a first source/drain epitaxial feature in contact with the plurality of semiconductor layers. The first source/drain epitaxial feature includes a bottom portion having substantially straight sidewalls. The structure further includes a spacer having a gate spacer portion and one or more source/drain spacer portions. Each source/drain spacer portion has a first height, and a source/drain spacer portion of the one or more source/drain spacer portions is in contact with one of the substantially straight sidewalls of the first source/drain epitaxial feature. The structure further includes a dielectric feature disposed adjacent one source/drain spacer portion of the one or more source/drain spacer portion. The dielectric has a second height substantially greater than the first height.

Semiconductor devices and methods of making the same include forming a gate structure on a thin semiconductor layer. Additional semiconductor material is formed on the thin semiconductor layer. The thin semiconductor layer is etched back and the additional semiconductor material to form source and drain regions and a channel region, with notches separating the source and drain region from the channel region.

A semiconductor device for power amplification includes: a source electrode, a drain electrode, and a gate electrode disposed above a semiconductor stack structure including a first nitride semiconductor layer and a second nitride semiconductor layer; and a source field plate that is disposed above the semiconductor stack structure between the gate electrode and the drain electrode, and has a same potential as a potential of the source electrode. The source field plate has a staircase shape, and even when length LF2 of an upper section is increased for electric field relaxation, an increase in parasitic capacitance Cds generated between the source field plate and a 2DEG surface is inhibited.

A semiconductor device includes: first and second fin structures, disposed on a substrate, that respectively extend in parallel to an axis; a first gate feature that traverses the first fin structure to overlay a central portion of the first fin structure; a second gate feature that traverses the second fin structure to overlay a central portion of the second fin structure; a first spacer comprising: a first portion comprising two layers that respectively extend from sidewalls of the first gate feature toward opposite directions of the axis; and a second portion comprising two layers that respectively extend from sidewalls of the first portion of the first spacer toward the opposite directions of the axis; and a second spacer comprising two layers that respectively extend from sidewalls of the second gate feature toward the opposite directions of the axis.

A semiconductor device includes a gate pattern crossing over a substrate, the gate pattern including a gate insulating layer, a gate electrode, and a gate capping pattern sequentially stacked on the substrate, a gate spacer covering a sidewall of the gate pattern, a source/drain pattern on the substrate, the source/drain pattern being adjacent to the sidewall of the gate pattern, a contact pad on the source/drain pattern, a top surface of the contact pad being lower than a top surface of the gate electrode, a source/drain contact plug on the contact pad, and a protection spacer between the gate spacer and the source/drain contact plug, the protection spacer having a ring shape enclosing the source/drain contact plug.

A semiconductor device includes first and second external dummy areas, and a circuit area between the first and second external dummy areas. The circuit area includes circuit active regions and circuit gate lines. Each external dummy area includes an external dummy active region and external dummy gate lines overlapping the external dummy active region and spaced apart from the circuit gate lines. The external dummy active region has a linear shape extending in a first horizontal direction or a shape including active portions isolated from direct contact with each other and extending sequentially in the first horizontal direction. The circuit active regions are between the first and second external dummy active regions and include a first plurality of circuit active regions extending sequentially in the first horizontal direction and a second plurality of circuit active regions extending sequentially in a second horizontal direction perpendicular to the first horizontal direction.