According to one embodiment, a semiconductor device includes first, second, third electrodes, a semiconductor member, and a first compound member. The third electrode is between the first and second electrodes in a first direction from the first to second electrodes. The semiconductor member includes first and second semiconductor regions. The first semiconductor region includes first, second, third, fourth, and fifth partial regions. A second direction from the first partial region to the first electrode crosses the first direction. The fourth partial region is between the first and third partial regions in the first direction. The fifth partial region is between the third and second partial regions in the first direction. The second semiconductor region includes first and second semiconductor portions. The first compound member includes first, second and third compound regions.

Methods of forming a ferroelectric material layer below a field plate for achieving increased V.sub.br with reduced R.sub.dson and resulting devices are provided. Embodiments include forming a N-Drift in a portion of the Si layer formed in a portion of a p-sub; forming an oxide layer over portions of the Si layer and the N-Drift; forming a gate over a portion of the oxide layer; forming a S/D extension region in the Si layer; forming first and second spacers on opposite sides of the gate and the oxide layer; forming a S/D region in the Si layer adjacent to the S/D extension region and a S/D region in the N-Drift remote from the Si layer; forming a U-shaped ferroelectric material layer over the oxide layer and the N-Drift, proximate or adjacent to the gate; and filling the U-shaped ferroelectric material layer with a metal, a field gate formed.

A semiconductor includes a gate stack over a substrate. The semiconductor device further includes an interlayer dielectric (ILD) at least partially enclosing the gate stack. The ILD includes a portion doped with a large species material, wherein the portion includes a first sidewall substantially perpendicular to a top-most surface of the ILD, and the portion includes a second sidewall having a positive angle with respect to the first sidewall.

A method of manufacturing a semiconductor device is disclosed. The method includes providing a substrate including a channel region for conducting current; shaping the substrate to form a protruding plane, a bottom plane and a side plane connected between the protruding plane and the bottom plane for the channel region; forming an oxide layer covering the channel region; forming a ferroelectric material strip, extending in a first direction, on a protruding plane of the oxide layer; and forming a gate strip, extending in a second direction orthogonal with the first direction, on the ferroelectric material strip and a side plane and a bottom plane of the oxide layer.

A integrated circuit structure comprises a fin extending from a substrate. The fin comprises source and drain regions and a channel region between the source and drain regions. A multilayer high-k gate dielectric stack comprises at least a first high-k material and a second high-k material, the first high-k material extending conformally over the fin over the channel region, and the second high-k material conformal to the first high-k material, wherein either the first high-k material or the second high-k material has a modified material property different from the other high-k material, wherein the modified material property comprises at least one of ferroelectricity, crystalline phase, texturing, ordering orientation of the crystalline phase or texturing to a specific crystalline direction or plane, strain, surface roughness, and lattice constant and combinations thereof. A gate electrode ix over and on a topmost high-k material in the multilayer high-k gate dielectric stack. A selector element is above the metal layer.

A semiconductor device includes a semiconductor substrate and a field effect transistor disposed on the semiconductor substrate. The field effect transistor includes a vertical fin defining a longitudinal length along a first axis, a width along a second axis and a vertical height along a third axis. The vertical fin includes source and drain regions separated by a gate region and a gate structure over the gate region. The gate structure includes a dipole layer and a gate electrode layer over the dipole layer. A first longitudinal section of the gate structure includes the dipole layer and a second longitudinal section of the gate structure is devoid of the dipole layer.

A semiconductor device includes: a first electrode; a first semiconductor layer of first conductivity type provided on the first electrode; a second semiconductor layer of first conductivity type provided on the first semiconductor layer; a first semiconductor region of second conductivity type provided on the second semiconductor layer; a second semiconductor region of first conductivity type provided on the first semiconductor region; a first insulating film provided in a trench reaching the second semiconductor layer from above the second semiconductor region via the second semiconductor region and the first semiconductor region, the first insulating film containing a first insulating material; a second electrode provided in the trench, the second electrode facing the second semiconductor layer via the first insulating film; a second insulating film provided between a position of 40% of a height of the second electrode from a lower end of the second electrode and a position of an upper end of the second electrode, the second insulating film being provided between the side surface of the second electrode and a fifth insulating film provided between a side surface of the second electrode and the second semiconductor layer, the fifth insulating film containing the first insulating material, the second insulating film containing a second insulating material having a higher dielectric constant than the first insulating material; a third electrode provided above the second electrode, the first insulating film and the second insulating film, the third electrode facing the first semiconductor region via a gate insulating film; an interlayer insulating film provided on the third electrode; and a fourth electrode provided above the interlayer insulating film, wherein the first insulating film in the trench below the position of 40% of the height of the second electrode contains only the first insulating material.

A method for fabricating a semiconductor device includes forming an interfacial layer and a dielectric layer on a base structure and around channels of a first gate-all-around field-effect transistor (GAA FET) device within a first region and a second GAA FET device within a second region, forming at least a scavenging metal layer in the first and second regions, and performing an anneal process after forming at least one cap layer.

According to one embodiment, a semiconductor device includes first, second and third electrodes, first and second semiconductor layers, a first member, and a first insulating member. The first semiconductor layer includes Al.sub.x1Ga.sub.1-x1N (0≤x1<1). The first semiconductor layer includes first, second, third, fourth, fifth, and sixth partial regions. The second semiconductor layer includes Al.sub.x2Ga.sub.1-x2N (0<x2—1, x1<x2). The second semiconductor layer includes first and second semiconductor portions. The first insulating member includes a first insulating region and includes a first material. The first insulating region contacts the third partial region and a part of the third electrode. The first member includes a first portion and includes a second material different from the first material. The first portion is between the fourth partial region and an other part of the third electrode.

Semiconductor devices including non-volatile memory transistors and methods of fabricating the same to improve performance thereof are provided. In one embodiment, the memory transistor comprises an oxide-nitride-oxide (ONO) stack on a surface of a semiconductor substrate, and a high work function gate electrode formed over a surface of the ONO stack. Preferably, the gate electrode comprises a doped polysilicon layer, and the ONO stack comprises multi-layer charge storing layer including at least a substantially trap free bottom oxynitride layer and a charge trapping top oxynitride layer. More preferably, the device also includes a metal oxide semiconductor (MOS) logic transistor formed on the same substrate, the logic transistor including a gate oxide and a high work function gate electrode. In certain embodiments, the dopant is a P+ dopant and the memory transistor comprises N-type (NMOS) silicon-oxide-nitride-oxide-silicon (SONOS) transistor while the logic transistor a P-type (PMOS) transistor. Other embodiments are also disclosed.