Devices with lower resistance and improved breakdown and method for producing the same

Abstract

Methods of forming a ferroelectric material layer below a field plate for achieving increased V.sub.br with reduced R.sub.dson and resulting devices are provided. Embodiments include forming a N-Drift in a portion of the Si layer formed in a portion of a p-sub; forming an oxide layer over portions of the Si layer and the N-Drift; forming a gate over a portion of the oxide layer; forming a S/D extension region in the Si layer; forming first and second spacers on opposite sides of the gate and the oxide layer; forming a S/D region in the Si layer adjacent to the S/D extension region and a S/D region in the N-Drift remote from the Si layer; forming a U-shaped ferroelectric material layer over the oxide layer and the N-Drift, proximate or adjacent to the gate; and filling the U-shaped ferroelectric material layer with a metal, a field gate formed.

Claims

1. A device comprising: a silicon (Si) layer in a portion of a p-type substrate (p-sub); a n-type drift region (N-Drift) in a portion of the Si layer; an oxide layer over adjacent portions of the Si layer and the N-Drift; a U-shaped ferroelectric material layer over a portion of the oxide layer and a portion of the N-Drift; a gate over the U-shaped ferroelectric material layer and the oxide layer; a first oxide liner adjacent to a sidewall of the gate and the oxide layer over Si layer and a second oxide liner adjacent to a sidewall of the gate, the ferroelectric material layer and the oxide layer over the N-Drift; a first spacer adjacent to the first oxide liner and over the Si layer and a second spacer adjacent to the second oxide liner and over the N-Drift; a source/drain (S/D) extension region in the Si layer under the first spacer; a S/D region in the Si layer adjacent to the S/D extension region and a S/D region in the N-Drift; a third oxide liner and fourth oxide liner over the oxide layer adjacent to a sidewall of the gate and the U-shaped ferroelectric material layer, respectively.

2. The device according to claim 1, wherein the ferroelectric material layer has a thickness of 7 nanometer (nm) to 20 nm.

3. The device according to claim 1, further comprising: a shallow trench isolation (STI) disposed in the N-Drift.

4. The device according to claim 1, wherein the U-shaped ferroelectric material layer is proximate to the gate.

5. The device according to claim 1, further comprising: a gap-filling material between the third oxide liner and the fourth oxide liner.

6. The device according to claim 4, wherein the U-shaped ferroelectric material layer comprises hafnium silicon oxide (HfSiO.sub.x), hafnium zirconium oxide (HfZrO.sub.2), or barium titanate (BaTiO.sub.3).

7. A device comprising: a silicon (Si) layer in a substrate; a n-type drift region (N-Drift) in a portion of the Si layer; an oxide layer over adjacent portions of the Si layer and the N-Drift; a gate over a portion of the oxide layer; a U-shaped ferroelectric material layer over the N-Drift; a field gate within the U-shaped ferroelectric material layer, an upper surface of the field gate coplanar with an upper surface of the U-shaped ferroelectric material layer; a first spacer adjacent to a first oxide liner and over the Si layer and a second spacer over the N-Drift on an opposite side of the gate remote from the Si layer; a second oxide liner between the U-shaped ferroelectric material layer and the second spacer over the N-Drift remote from the first oxide liner; a source/drain (S/D) extension region in the Si layer under the first spacer; a S/D region in the Si layer adjacent to the S/D extension region and the S/D region in the N-Drift remote from the Si layer; a third oxide liner and fourth oxide liner over the oxide layer adjacent to a sidewall of the gate and the U-shaped ferroelectric material layer, respectively; and a gap-filling material between the third oxide liner and the fourth oxide liner.

8. The device according to claim 7, wherein the gate comprises a metal.

9. The device according to claim 7, further comprising: the first oxide liner adjacent to a sidewall of the gate and the oxide layer over the Si layer.

10. The device according to claim 7, wherein the U-shaped ferroelectric material layer is proximate to the gate.

11. The device according to claim 7, further comprising: a shallow trench isolation (STI) in the N-drift below the field gate.

12. The device according to claim 7, wherein the U-shaped ferroelectric material layer comprises hafnium silicon oxide (HfSiO.sub.x), hafnium zirconium oxide (HfZrO.sub.2), or barium titanate (BaTiO.sub.3).

13. The device according to claim 7, wherein the U-shaped ferroelectric material layer has a thickness of 7 nanometer (nm) to 20 nm.

14. The device according to claim 9, wherein the field gate comprises a metal.

15. A device comprising: a silicon (Si) layer in a portion of a p-type substrate (p-sub); a n-type drift region (N-Drift) in a portion of the Si layer; an oxide layer over adjacent portions of the Si layer and the N-Drift; a ferroelectric material layer over a portion of the oxide layer and a portion of the N-Drift; a gate over the ferroelectric material layer and the oxide layer; a first oxide liner adjacent to a sidewall of the gate and the oxide layer over Si layer and a second oxide liner adjacent to a sidewall of the gate, the ferroelectric material layer and the oxide layer over the N-Drift; a first spacer adjacent to the first oxide liner and over the Si layer and a second spacer adjacent to the second oxide liner and over the N-Drift; a source/drain (S/D) extension region in the Si layer under the first spacer; a shallow trench isolation (STI) in the N-Drift below a portion of the ferroelectric material layer and below a portion of the gate, when viewed in cross-section; a S/D region in the Si layer adjacent to the S/D extension region and the S/D region in the N-Drift; a third oxide liner and fourth oxide liner over the oxide layer adjacent to a sidewall of the gate and the ferroelectric material layer, respectively; and a gap-filling material between the third oxide liner and the fourth oxide liner.

16. The device according to claim 15, wherein the ferroelectric material layer is U-shaped and has a thickness of 7 nanometer (nm) to 20 nm.

17. The device according to claim 15, wherein the ferroelectric material layer comprises hafnium silicon oxide (HfSiO.sub.x), hafnium zirconium oxide (HfZrO.sub.2), or barium titanate (BaTiO.sub.3).

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The present disclosure is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawing and in which like reference numerals refer to similar elements and in which:

(2) FIGS. 1 through 4 schematically illustrate cross-sectional views of a process flow for forming a HV gate with an enhanced field gate, in accordance with an exemplary embodiment;

(3) FIGS. 5 through 8 schematically illustrate cross-sectional views of a process flow for forming a common HV gate with dual dielectric, in accordance with an exemplary embodiment; and

(4) FIGS. 9 through 12 schematically illustrate cross-sectional views of a process flow for forming a HV gate with a side replacement field gate, in accordance with an exemplary embodiment.

DETAILED DESCRIPTION

(5) In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of exemplary embodiments. It should be apparent, however, that exemplary embodiments may be practiced without these specific details or with an equivalent arrangement. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring exemplary embodiments. In addition, unless otherwise indicated, all numbers expressing quantities, ratios, and numerical properties of ingredients, reaction conditions, and so forth used in the specification and claims are to be understood as being modified in all instances by the term “about.”

(6) The present disclosure addresses and solves the current problem of higher R.sub.dson while attaining higher V.sub.br attendant upon reduced doping in the N-Drift region. The problem is solved, inter alia, by forming a U-shaped ferroelectric material layer below a field plate to achieve lower R.sub.dson and higher V.sub.br through enhanced modulation of surface electric field and resistance by using ferroelectric engineering.

(7) Methodology in accordance with embodiments of the present disclosure includes forming a Si layer in a portion of a p-sub. An N-Drift is formed in a portion of the Si layer. An oxide layer is formed over adjacent portions of the Si layer and the N-Drift. A gate is formed over a portion of the oxide layer. An S/D extension region is formed in the Si layer. A first spacer and a second spacer are formed on opposite sides of the gate. An S/D region is formed in the Si layer adjacent to the S/D extension region and an S/D region in the N-Drift. A U-shaped ferroelectric material layer is formed over the oxide layer, and the N-Drift proximate or adjacent to the gate, and the U-shaped ferroelectric material layer is filled with a metal to form a field gate.

(8) Still other aspects, features, and technical effects will be readily apparent to those skilled in this art from the following detailed description, wherein preferred embodiments are shown and described, simply by way of illustration of the best mode contemplated. The disclosure is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.

(9) FIGS. 1 through 4 schematically illustrate cross-sectional views of a process flow for forming a HV gate with an enhanced field gate, in accordance with an exemplary embodiment. Referring to FIG. 1, a Si layer 101 is formed, e.g., to a thickness of 0.1 micrometer (μm) to 5 μm, over the p-sub 103. In one instance, the Si layer 101 is a high-voltage p-type well (HVPW). In another instance, the Si layer 101 may also be formed of gallium nitride (GaN) or any high resistivity materials. In a further instance, the Si layer 101 is p-type doped with boron (B) or indium (In). Then, an N-Drift 105 is formed, e.g., of Si or GaN or any high resistivity materials to a thickness of 0.1 μm to 5 μm, in a portion of the Si layer 101. In one instance, the N-Drift 105 is n-type doped with phosphorus (P) or arsenic (As). Next, an STI 107 is formed in a portion of the N-Drift 105. In one instance, the STI 107 is optional and may be formed before the Si layer 101. Subsequently, an oxide layer 201 is formed over the Si layer 101, the N-Drift 105 and the STI 107, as depicted in FIG. 2. In one instance, the oxide layer 201 is a high voltage oxide (HVOX), e.g., a thicker oxide ranging from 10 nm to 200 nm depending on voltage requirements. Then, a polysilicon layer (not shown for illustrative convenience) is formed over the oxide layer 201. Next, portions of the polysilicon layer over the Si layer 101 and the N-Drift 105 are removed down to the oxide layer 201, the remaining portion of the polysilicon layer over the Si layer 101 and N-Drift 105 forms a gate 203 and a dummy field gate 205, respectively. In one instance, the gate 203 is a HV gate. Thereafter, in FIG. 3, oxide liners 301 are formed, e.g., of high-temperature oxide (HTO) to a thickness of 0.2 nm to 5 nm and a width of 0.2 nm to 5 nm by a low pressure chemical vapor deposition (LPCVD) or a plasma enhanced chemical vapor deposition (PECVD), on the sidewalls of the gate 203 and the dummy field gate 205 and over portions of the oxide layer 201. Then, an S/D extension region 303 is formed in the Si layer 101 under the oxide layer 201. In one instance, the S/D extension region 303 may be formed before forming the oxide liners 301. Next, a silicon nitride (SiN) or an oxide layer (not shown for illustrative convenience) is conformally formed over the oxide layer 201, the oxide liners 301, the gate 203 and the dummy field gate 205. In one instance, the thickness of the SiN or oxide layer is at least equal to or more than half of the gap between the two neighboring oxide liners 301 such that the SiN or oxide layer completely fills the gap through pinch-off. Subsequently, the SiN or oxide layer is etched, e.g., by a directional dry etch process, forming spacers 305, 307 and 309 on the sidewall of the oxide liners 301 and over the oxide layer 201. Then, an S/D region 311 is formed in the Si layer 101 and an S/D region 313 is formed in the N-Drift 105. In one instance, the spacer 307 may include two spacers with inter layer dielectric (ILD) in-between (not shown for illustrative convenience). In this instance, the ILD is formed by a conventional back-end-of-line (BEOL) process filling a gap between the two spacers. Subsequently, a CMP is performed to planarize the surface. In such case, the field gate 205 may be connected individually to a separate bias or to the HV gate 203 or to the S/D region 311 through metal connections.

(10) Referring to FIG. 4, the dummy field gate 205 between the oxide liners 301 is removed exposing the oxide layer 201 and a cavity (not shown for illustrative convenience) is formed. Next, a U-shaped ferroelectric material layer 401 is formed, e.g., of HfSiO.sub.x, HfZrO.sub.2, BaTiO.sub.3 or any other suitable ferroelectric materials to a thickness of 7 nm to 20 nm, over the exposed oxide layer 201 and on sidewalls of the cavity. Subsequently, the U-shaped ferroelectric material layer 401 is filled with metal, thereby forming a field gate 403. In this instance, the upper surface of the field gate 403 is coplanar with the upper surface of the U-shaped ferroelectric material layer 401, e.g., as a result of CMP. In one instance, rather than filling U-shaped ferroelectric material layer 401 with metal, the U-shaped ferroelectric material layer 401 is filled with polysilicon. In one instance, reduced surface electric field is achieved through gate 203 coupling or bias, wherein the field gate 403 is shorted to the gate 203. When the gate 203 is turned-on to a positive bias, it is coupled to the field gate 403, and the ferroelectric material layer 401 amplifies the voltage, e.g., by 25%, thereby allowing lower resistance. In addition, the field gate 403 may be biased to a negative voltage during off-state and to a positive voltage during on-state, the voltage may be amplified both ways through the ferroelectric material layer 401 to further reduce the electric field during off-state and accumulate carriers during on-state.

(11) FIGS. 5 through 8 schematically illustrate cross-sectional views of a process flow for forming a common HV gate with dual dielectric, in accordance with an exemplary embodiment. The process steps of FIG. 5 are identical to the process steps of FIG. 1. Referring to FIG. 6, an oxide layer 601 is formed over portions of the Si layer 101, the N-Drift 105 and the STI 107. Then, a ferroelectric material layer 603 is formed, e.g., of HfSiO.sub.x, HfZrO.sub.2, BaTiO.sub.3 or any other suitable ferroelectric materials to a thickness of 5 nm to 200 nm, over a portion of the oxide layer 601 over the N-Drift 105. Next, a polysilicon layer (not shown for illustrative convenience) is formed over the oxide layer 601 and the ferroelectric material layer 603. Subsequently, portions of the polysilicon layer, the oxide layer 601 and the ferroelectric material layer 603 are removed, thereby forming a gate 701 over the ferroelectric material layer 603′ and a portion of the oxide layer 601′, as depicted in FIG. 7. In one instance, the gate 701 is a HV gate. As illustrated, the oxide layer 601′ is aligned to the edges of the gate 701 after etching. Next, in FIG. 8, an S/D extension region 801 is formed in the Si layer 101. Then, oxide liners 803 are formed, e.g., of HTO to a thickness of 0.2 nm to 5 nm and a width of 0.2 nm to 5 nm by LPCVD or PECVD, on the sidewalls of the gate 701, the oxide layer 601′ and one of the sidewall of the ferroelectric material layer 603′ over the Si layer 101 and the N-Drift 105, respectively. Subsequently, spacers 805 are formed on the sidewalls of the oxide liners 803 and over the Si layer 101 and the N-Drift 105 following a similar process flow as described in FIGS. 1 through 4. Then, S/D regions 807 and 809 are formed in the Si layer 101 and the N-Drift 105, respectively.

(12) FIGS. 9 through 12 schematically illustrate cross-sectional views of a process flow for forming a HV gate with a side replacement field gate, in accordance with an exemplary embodiment. The process steps of FIG. 9 are identical to the process steps of FIGS. 1 and 5. Referring to FIG. 10, an oxide layer 1001 is formed over the Si layer 101, the N-Drift 105 and the STI 107. Then, a polysilicon layer (not shown for illustrative convenience) is formed over the oxide layer 1001. Subsequently, portions of the polysilicon layer and the oxide layer 1001 are removed, thereby forming a gate 1003 over a portion of the oxide layer 1001′. As illustrated, the oxide layer 1001′ is aligned to the edges of the gate 1003 after etching. Next, an S/D extension region 1101 is formed in the Si layer 101, as depicted in FIG. 11. Then, oxide liners 1103 are formed on the sidewalls of the gate 1003 and the oxide layer 1001′ over the Si layer 101 and the N-Drift 105, respectively. Subsequently, spacers 1105 are formed on the sidewalls of the oxide liners 1103 and over the over the Si layer 101 and the N-Drift 105 following a similar process flow as described in FIGS. 1 through 4. Then, S/D regions 1107 and 1109 are formed in the Si layer 101 and the N-Drift 105, respectively.

(13) Referring to FIG. 12, a mask layer (not shown for illustrative convenience) is formed, e.g., of ILD, over the gate 1003. Next, a portion of the mask layer is removed down to an upper surface of the gate 1003 over the N-Drift 105. Subsequently, the exposed portion of the gate 1003 is removed down to the oxide layer 1001′, thereby forming a cavity (not shown for illustrative convenience). Thereafter, a U-shaped ferroelectric material layer 1201 is formed, e.g., to a thickness of 7 nm to 20 nm, over and on sidewalls of the cavity. Subsequently, the U-shaped ferroelectric material layer 1201 is filled with metal, thereby forming a field gate 1203. In this instance, the upper surface of the field gate 1203 is coplanar with the upper surface of the U-shaped ferroelectric material layer 1201, e.g., by CMP.

(14) The embodiments of the present disclosure can achieve several technical effects, including a significantly amplified voltage, e.g., by more than 25%, through the ferroelectric material to reduce the surface electric field in off-state and reduce the R.sub.dson in on-state. In addition, the present disclosure can achieve an enhanced R.sub.dson−V.sub.br performance. Further, the ferroelectric material may be freely employed by the core logic, otherwise a minimal cost of depositing and annealing the ferroelectric material is required. Devices formed in accordance with embodiments of the present disclosure enjoy utility in various industrial applications, e.g., microprocessors, smart phones, mobile phones, cellular handsets, set-top boxes, DVD recorders and players, automotive navigation, printers and peripherals, networking and telecom equipment, gaming systems, and digital cameras. The present disclosure enjoys industrial applicability in any of various types of highly integrated MV to HV semiconductor devices.

(15) In the preceding description, the present disclosure is described with reference to specifically exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the present disclosure, as set forth in the claims. The specification and drawings are, accordingly, to be regarded as illustrative and not as restrictive. It is understood that the present disclosure is capable of using various other combinations and embodiments and is capable of any changes or modifications within the scope of the inventive concept as expressed herein.