The present disclosure generally to semiconductor devices, and more particularly to semiconductor devices having high-voltage transistors integrated on a semiconductor-on-insulator substrate and methods of forming the same. The present disclosure provides a semiconductor device including a semiconductor-on-insulator (SOI) substrate having a semiconductor layer, a bulk substrate and an insulating layer between the semiconductor layer and the bulk substrate, a source region and a drain region disposed on the bulk substrate, an isolation structure extending through the insulating layer and the semiconductor layer and terminates in the bulk substrate, and a gate structure between the source region and the drain region, the gate structure is disposed on the semiconductor layer.

Provided are electronic devices and methods of manufacturing the same. An electronic device may include a substrate, a gate electrode on the substrate, a ferroelectric layer between the substrate and the gate electrode, and a carbon layer between the substrate and the ferroelectric layer. The carbon layer may have an sp.sup.2 bonding structure.

Semiconductor devices and methods of manufacturing are presented wherein a gate dielectric is treated within an analog region of a semiconductor substrate. The gate dielectric may be treated with a plasma exposure and/or an annealing process in order to form a recovered region of the gate dielectric. A separate gate dielectric is formed within a logic region of the semiconductor substrate, and a first gate electrode and second gate electrode are formed over the gate dielectrics.

Some embodiments of a method for manufacturing integrated circuits include the operations of forming a back gate structure on a substrate, forming a memory layer over the back gate structure, forming a buffer layer over the memory layer, forming a conductive channel over the buffer layer, and forming source/drain regions over the conductive channel. In some embodiments, a second buffer layer is formed between the back gate structure and the memory layer.

A semiconductor memory device according to an embodiment includes: a semiconductor layer extending in a first direction; a first gate electrode layer; a first insulating layer between the semiconductor layer and the first gate electrode layer; a second insulating layer between the first insulating layer and the first gate electrode layer, the second insulating layer having a first portion containing a ferroelectric material; and a first layer between the first insulating layer and the second insulating layer, the first layer containing silicon, nitrogen, and fluorine, the first layer having a first region and a second region between the first region and the second insulating layer, the first layer having a second atomic ratio of nitrogen to silicon in the second region higher than a first atomic ratio of nitrogen to silicon in the first region, and the first layer having fluorine concentration higher than the second region.

The present disclosure relates to an integrated chip. The integrated chip includes a source region and a drain region disposed within an upper surface of a substrate. One or more dielectric materials are disposed within a trench defined by sidewalls of the substrate that surround the source region and the drain region. The one or more dielectric materials include one or more interior surfaces defining a recess within the one or more dielectric materials. A gate structure is disposed over the substrate between the source region and the drain region. The gate structure includes a first gate material over the upper surface of the substrate and a second gate material. The second gate material completely fills the recess as viewed along a cross-sectional view.

A method includes simultaneously forming a first dummy gate stack and a second dummy gate stack on a first portion and a second portion of a protruding fin, simultaneously removing a first gate electrode of the first dummy gate stack and a second gate electrode of the second dummy gate stack to form a first trench and a second trench, respectively, forming an etching mask, wherein the etching mask fills the first trench and the second trench, patterning the etching mask to remove the etching mask from the first trench, removing a first dummy gate dielectric of the first dummy gate stack, with the etching mask protecting a second dummy gate dielectric of the second dummy gate stack from being removed, and forming a first replacement gate stack and a second replacement gate stack in the first trench and the second trench, respectively.

A non-volatile memory device includes a substrate. A plurality of shallow trench isolation (STI) lines are disposed on the substrate and extend along a first direction. A memory gate structure is disposed on the substrate between adjacent two of the plurality of STI lines. A trench line is disposed in the substrate and extends along a second direction intersecting the first direction, wherein the trench line also crosses top portions of the plurality of STI lines. A conductive line is disposed in the trench line and used as a selection line to be coupled to the memory gate structure.

The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a first active region and a second fin active region extruded from a semiconductor substrate; an isolation featured formed in the semiconductor substrate and being interposed between the first and second fin active regions; a dielectric gate disposed on the isolation feature; a first gate stack disposed on the first fin active region and a second gate stack disposed on the second fin active region; a first source/drain feature formed in the first fin active region and interposed between the first gate stack and the dielectric gate; a second source/drain feature formed in the second fin active region and interposed between the second gate stack and the dielectric gate; a contact feature formed in a first inter-level dielectric material layer and landing on the first and second source/drain features and extending over the dielectric gate.

A domain switching device includes a channel region, a source region and a drain region connected to the channel region, a gate electrode isolated from contact with the channel region, an anti-ferroelectric layer between the channel region and the gate electrode, a conductive layer between the gate electrode and the anti-ferroelectric layer to contact the anti-ferroelectric layer, and a barrier layer between the anti-ferroelectric layer and the channel region.