An object of the present invention is to provide stable withstand voltage characteristics, reduce turn-off losses along with a reduction in leakage current when the device is off, improve controllability of turn-off operations, and improve blocking capability at turn-off. An N buffer layer includes a first buffer layer joined to an active layer and having one peak in impurity concentration, and a second buffer layer joined to the first buffer layer and an N.sup. drift layer, having at least one peak point in impurity concentration, and having a lower maximum impurity concentration than the first buffer layer. The impurity concentration at the peak point of the first buffer layer is higher than the impurity concentration of the N.sup. drift layer, and the impurity concentration of the second buffer layer is higher than the impurity concentration of the N.sup. drift layer in the entire area of the second buffer layer.

The present disclosure provides a silicon-controlled rectifier structure and a manufacturing method therefor. The silicon-controlled rectifier structure comprises a substrate; and an N-Well and a P-Well in the substrate, wherein an N-type heavily-doped region 410 and a P-type heavily-doped region 422 which are connected to an anode are provided in the N-Well, and a floating guard ring 416 is further provided in the N-Well between the N-type heavily-doped region 410 and the P-type heavily-doped region 422, the guard ring being spaced from the N-type heavily-doped region 410 by a shallow trench isolation, and an active area having a predetermined width exists between the guard ring and the P-type heavily-doped region 422; and an N-type heavily-doped region 414 and a P-type heavily-doped region 424 which are connected to a cathode are provided in the P-Well.

A TVS device may include a substrate, comprising a polarity of a first type, a first dopant layer, disposed on a first main surface of the substrate, and comprising a polarity of a second type, wherein the first dopant layer forms a P/N junction with the substrate. The TVS device may further include a second dopant layer, disposed on a second main surface of the substrate, opposite the first main surface, the second layer comprising the polarity of the first type, and a patterned layer, disposed on the second main surface of the substrate, the patterned layer comprising the polarity of the second type, wherein the patterned layer is interspersed with the second layer.

Techniques for co-integrating gate-all-around nanosheet devices having bottom dielectric isolation with an ideal vertical P-N-P diode on a common substrate are provided. In one aspect, a semiconductor structure includes: a diode in a first region of a bulk substrate, where the diode includes P-N-P vertical implanted layers present in the bulk substrate, and a single source/drain region epitaxial material disposed on the P-N-P vertical implanted layers; and a nanosheet device with a bottom dielectric isolation layer in a second region of the bulk substrate. The nanosheet device can include nanosheet channels and gates that surround a portion of each of the nanosheet channels in a gate-all-around configuration. A method of fabricating the present semiconductor structures is also provided.

A method of manufacturing a semiconductor structure forming a first diffusion layer on a first electrode layer and forming a core layer over the first diffusion layer. A second diffusion layer is formed over the core layer. A plurality of diffusion regions are formed in the second diffusion layer. A second electrode layer is formed over the second diffusion layer and in contact with the plurality of diffusion regions. The second diffusion layer is coupled to the plurality of diffusion regions through the second electrode layer. The substrate is sandwiched between the first electrode layer and the second electrode layer.

A semiconductor device may include at least one double-barrier resonant tunneling diode (DBRTD). The at least one DBRTD may include a first doped semiconductor layer and a first barrier layer on the first doped semiconductor layer and including a superlattice. The superlattice may include stacked groups of layers, each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The at least one DBRTD may further include an intrinsic semiconductor layer on the first barrier layer, a second barrier layer on the intrinsic semiconductor layer, and a second doped semiconductor layer on the second superlattice layer.

A semiconductor element capable of adjusting a barrier height .sub.Bn and performing zero-bias operation and impedance matching with an antenna for improving detection sensitivity of high-frequency RF electric signals, a method of manufacturing the same, and a semiconductor device having the same. In the semiconductor element, a concentration of InGaAs (n-type InGaAs layer) is intentionally set to be high over a range for preventing the change of the barrier height caused by the bias described above up to a deep degeneration range. An electron Fermi level (E.sub.F) increases from a band edge of InGaAs (n-type InGaAs layer) to a band edge of InP (InP depletion layer).

A semiconductor device includes: a semiconductor substrate having a cell region in which a device is provided, and a termination region provided around the cell region; a first insulating film provided on the semiconductor substrate in the termination region and having a plurality of openings; a plurality of metal electrodes provided in the termination region and connected to the semiconductor substrate via the plurality of openings; and a second insulating film having lower coefficient of moisture absorption than that of the first insulating film and covering the first insulating film and the plurality of metal electrodes, wherein the second insulating film is in direct contact with the semiconductor substrate in a region from the outermost electrode of the plurality of metal electrodes to an end part of the semiconductor substrate.

To prevent an intermediate region from contacting a cathode electrode even if a cathode region is partially defective. There is provided a semiconductor device with a semiconductor substrate that has a field stop region where first impurities of a first conduction type are implanted, an intermediate region that is formed on a back surface side of the field stop region and where second impurities of a second conduction type are implanted, and a cathode region of the first conduction type that is formed on a back surface side of the intermediate region. In a back surface of the semiconductor substrate, a concentration of the first impurities is higher than a concentration of the second impurities.

A semiconductor device is provided that includes a first n+ region, a first p+ region within the first n+ region, a second n+ region, a second p+ region, positioned between the first n+ region and the second n+ region. The first n+ region, the second n+ region and the second p+ region are positioned within a p? region. A first space charge region and a second space charge region are formed within the p? region. The first space region is positioned between the first n+ region and the second p+ region, and the second space region is positioned between the second p+ region and the second n+ region.