A semiconductor device having a fast recovery diode (FRD) is provided. The semiconductor device includes a substrate, a first well region disposed in the substrate, a base region disposed in the first well region, a first impurity region of a first conductivity type disposed in the base region, a second impurity region of a second conductivity type disposed in the first well region and separated from the base region, a first electrode electrically connected to the base region and the first impurity region, and a second electrode electrically connected to the second impurity region.

The present disclosure relates to semiconductor structures and, more particularly, to high performance silicon controlled rectifier (SCR) devices and methods of manufacture. The structure includes: a first well in a semiconductor substrate; a second well in the semiconductor substrate, adjacent to the first well; a plurality of shallow trench isolation structures extending into the first well and the second well; and a deep trench isolation structure between the plurality of shallow trench isolation structures and extending into the semiconductor material deeper than the plurality of shallow trench isolation structures.

A diode device of a transient voltage suppressor (TVS) is disclosed. The diode device includes a substrate, a first well, a second well, a first electrode and a second electrode. The substrate has a first surface. The first well is formed in the substrate and near the first surface. The second well is formed in the substrate and near the first surface. There is a gap between the first well and the second well. The first electrode is electrically connected with the first well. The second electrode is electrically connected with the second well. A current path is formed from the first electrode, the first well, the substrate, the second well to the second electrode. The current path passes through a plurality of PN junctions to form an equivalent circuit having a plurality of equivalent capacitances coupled in series.

A semiconductor device and a method of forming the same are provided. The semiconductor device includes a first substrate, a capacitor within the first substrate, a diode structure within the first substrate adjacent the capacitor, and a first interconnect structure over the capacitor and the diode structure. A first conductive via of the first interconnect structure electrically couples the capacitor to the diode structure.

A method of producing a four-layer silicon diode, including selecting a first silicon wafer, wherein said first silicon wafer is CZ-grown B-doped with <100> orientation, a resistivity of less than 0.01 Ohm-cm, and an oxygen content of greater than 10 ppma, and then selecting a second silicon wafer, wherein said second silicon wafer is CZ-grown P-doped with <100> orientation, a resistivity of less than 0.005 Ohm-cm, and an oxygen content of greater than 10 ppma, followed by cleaning the respective first and second silicon wafers. The wafers are then HF treated to yield respective first and second cleaned wafers, the first cleaned wafer is positioned into a first furnace and the second cleaned wafer is positioned into a second furnace, wherein the first and second furnaces are not unitary. Next is annealing the respective first and second cleaned wafers in a reducing atmosphere to yield respective first and second respective out-diffused gradient wafers, followed by bonding together respective first and second heat-treated wafers to yield a mated and/or bonded four-layer substrate having a first heavy doped n-type layer, a second gradient doped n-type layer, a third gradient doped p-type layer, and a fourth heavy doped p-type layer.

A method for manufacturing a merged PiN Schottky (MPS) diode may include steps of providing a substrate having a first conductivity type; forming an epitaxial layer with the first conductivity type on top of the substrate; forming a plurality of regions with a second conductivity type under a top surface of the epitaxial layer; forming a plasma spreading layer; depositing and patterning a first Ohmic contact metal on the regions with the second conductivity type; depositing a Schottky contact metal on top of the entire epitaxial layer; and forming a second Ohmic contact metal on a backside of the substrate. In another embodiment, the step of forming a plurality of regions with a second conductivity type may include steps of depositing and patterning a mask layer on the epitaxial layer, implanting P-type dopant into the epitaxial layer, and removing the mask layer.

In one embodiment, an overvoltage protection device may include a semiconductor substrate comprising an n-type body region. The overvoltage protection device may further include a first p-type region disposed in a first surface region of the semiconductor substrate, and forming a first P/N junction with the n-type body region, and a second p-type region disposed in a second surface region of the semiconductor substrate opposite the first surface, and forming a second P/N junction with the n-type body region, wherein the n-type body region, first p-type region, and second p-type region form a breakdown device having a breakdown voltage greater than 100V when an external voltage is applied between the first surface region and second surface region.

A method of regrowing material includes providing a III-nitride structure including a masking layer and patterning the masking layer to form an etch mask. The method also includes removing, using an in-situ etch, a portion of the III-nitride structure to expose a regrowth region and regrowing a III-nitride material in the regrowth region.

The present disclosure relates to a symmetrical, punch-through transient voltage suppression (TVS) device includes a mesa structure disposed on a semiconductor substrate. The mesa structure includes a first semiconductor layer of a first conductivity-type, a second semiconductor layer of a second conductivity-type disposed on the first semiconductor layer, and a third semiconductor layer of the first conductive-type disposed on the second semiconductor layer. The mesa structure also includes beveled sidewalls forming mesa angles with respect to the semiconductor substrate and edge implants disposed at lateral edges of the second semiconductor layer. The edge implants including dopants of the second conductive-type are configured to cause punch-through to occur in a bulk region and not in the lateral edges of the second semiconductor layer.

The present disclosure relates to a symmetrical, punch-through transient voltage suppression (TVS) device includes a mesa structure disposed on a semiconductor substrate. The mesa structure includes a first semiconductor layer of a first conductivity-type, a second semiconductor layer of a second conductivity-type disposed on the first semiconductor layer, and a third semiconductor layer of the first conductive-type disposed on the second semiconductor layer. The mesa structure also includes beveled sidewalls forming mesa angles with respect to the semiconductor substrate and edge implants disposed at lateral edges of the second semiconductor layer. The edge implants including dopants of the second conductive-type are configured to cause punch-through to occur in a bulk region and not in the lateral edges of the second semiconductor layer.