A semiconductor device and a method of forming the same are provided. The semiconductor device includes a first substrate, a capacitor within the first substrate, a diode structure within the first substrate adjacent the capacitor, and a first interconnect structure over the capacitor and the diode structure. A first conductive via of the first interconnect structure electrically couples the capacitor to the diode structure.

An electronic device includes a first-conductivity-type substrate and a second-conductivity-type epitaxial layer having a first dopant concentration. A first substrate region includes a second-conductivity-type buried layer and is enclosed by a first deep isolation structure. Within the first substrate region are a first doped region having the second conductivity type and a dopant concentration greater than the first dopant concentration and a second doped region having the first conductivity type. A second substrate region includes a first-conductivity-type buried layer and is enclosed by a second deep isolation structure. Within the second substrate region is a third doped region having the second conductivity type and a dopant concentration greater than the first dopant concentration.

Embodiment relates to the field of semiconductor technologies, and proposes a semiconductor device and a fabrication method thereof. The semiconductor device includes: a substrate, a semiconductor structure, an insulating layer, and a conductive layer. The semiconductor structure is positioned on a side of the substrate and includes a first semiconductor structure and a second semiconductor structure, wherein the first semiconductor structure and the second semiconductor structure form a PN junction. The insulating layer is positioned on a side of the semiconductor structure facing away from the substrate. The conductive layer is positioned on a side of the insulating layer facing away from the substrate, and an orthographic projection of the conductive layer on the substrate at least partially overlaps an orthographic projection of the PN junction on the substrate.

A semiconductor device includes a semiconductor layer of a first conductivity type having a device forming region and an outside region, an impurity region of a second conductivity type formed in a surface layer portion of a first main surface in the device forming region, a field limiting region of a second conductivity type formed in the surface layer portion in the outside region and having a impurity concentration higher than that of the impurity region, and a well region of a second conductivity type formed in a region between the device forming region and the field limiting region in the surface layer portion in the outside region, having a bottom portion positioned at a second main surface side with respect to bottom portions of the impurity region and the field limiting region, and having a impurity concentration higher than that of the impurity region.

An electronic device, e.g. integrated circuit, has an n-type region and a p-type region located within a semiconductor substrate, the n-type region and the p-type region each intersecting the substrate surface. A dielectric structure is located directly on the substrate surface. The dielectric structure has first and second laterally opposed sides, with the first side located over the n-type region and the second side located over the p-type region.

A power device includes a substrate including a drift layer and having a first region and a second region, the drift layer having impurities of a first type; a switch formed in the first region; a diode formed in the second region; a metal structure formed over a surface of the substrate, the metal structure having a first thickness over the first region of the substrate and a second thickness over the second region of the substrate, the first thickness and second thickness having at least 3 um in thickness difference; and a zone provided in the drift layer in the second region of the substrate, the zone having impurities of a second type that is different from the first type.

A semiconductor device including a protected element, an element isolation region, a contact region, and a shield region. The protected element is configured including a p-n junction diode between an anode region and a cathode region, and is arranged in an active layer of a substrate. A periphery of the diode is surrounded by the element isolation region. The contact region is arranged at a portion on a main face of the anode region, is set with a same conductivity type as the anode region, and is set with a higher impurity concentration than the anode region. The shield region is arranged between the cathode region and the contact region so as to extend from the main face of the anode region as far as a region deeper than a depth of the contact region and shallower than the anode region. The shield region is configured including a semiconductor region with an opposite conductivity type to the anode region.

An edge delimits a semiconductor body in a direction parallel to a first side of the semiconductor body. A peripheral area is arranged between the active area and edge. A first semiconductor region of a first conductivity type extends from the active area into the peripheral area. A second semiconductor region of a second conductivity type forms a pn-junction with the first semiconductor region. A first edge termination region of the second conductivity type arranged at the first side adjoins the first semiconductor region, between the second semiconductor region and edge. A second edge termination region of the first conductivity type arranged at the first side and between the first edge termination region and edge has a varying concentration of dopants of the first conductivity type which increases at least next to the first edge termination region substantially linearly with an increasing distance from the first edge termination region.

A semiconductor device includes a semiconductor layer of a first conductivity type having a device forming region and an outside region, an impurity region of a second conductivity type formed in a surface layer portion of a first main surface in the device forming region, a field limiting region of a second conductivity type formed in the surface layer portion in the outside region and having a impurity concentration higher than that of the impurity region, and a well region of a second conductivity type formed in a region between the device forming region and the field limiting region in the surface layer portion in the outside region, having a bottom portion positioned at a second main surface side with respect to bottom portions of the impurity region and the field limiting region, and having a impurity concentration higher than that of the impurity region.

Some embodiments of the disclosure provide a semiconductor device. The semiconductor device includes: a doped substrate; a barrier layer, disposed on the doped substrate; a channel layer, disposed between the doped substrate and the barrier layer; and a doped semiconductor structure, disposed in the doped substrate, where a band gap of the barrier layer is greater than a band gap of the channel layer, the doped substrate and the doped semiconductor structure have different polarities, and the doped substrate includes a doped silicon substrate.