A method for manufacturing an optical device includes providing a carrier waver, provide a first substrate having a first surface region, and forming a first gallium and nitrogen containing epitaxial material overlying the first surface region. The first epitaxial material includes a first release material overlying the first substrate. The method also includes patterning the first epitaxial material to form a plurality of first dice arranged in an array; forming a first interface region overlying the first epitaxial material; bonding the first interface region of at least a fraction of the plurality of first dice to the carrier wafer to form bonded structures; releasing the bonded structures to transfer a first plurality of dice to the carrier wafer, the first plurality of dice transferred to the carrier wafer forming mesa regions on the carrier wafer; and forming an optical waveguide in each of the mesa regions, the optical waveguide configured as a cavity to form a laser diode of the electromagnetic radiation.

A method for producing a protection device and a protection device are disclosed. The method includes: forming a first diode arrangement including at least one first diode and at least one second diode connected in anti-series between a first circuit node and a second circuit node of the first diode arrangement; forming a second diode arrangement including at least one first diode and at least one second diode connected in anti-series between a first circuit node and a second circuit node of the second diode arrangement; and connecting the second circuit node of the first diode arrangement and the second circuit node of the second diode arrangement.

According to the disclosure, a semiconductor device includes a semiconductor substrate including an IGBT region and a diode region, a first electrode provided on an upper surface of the semiconductor substrate and a second electrode provided on a back surface of the semiconductor substrate, wherein the diode region includes an n-type drift layer, a p-type anode layer provided on an upper surface side of the drift layer, and an n-type cathode layer provided on a back surface side of the drift layer, a lifetime control region having crystal defect density higher than crystal defect density of other portions of the drift layer and including protons is provided on a back surface side relative to a center in a thickness direction of the semiconductor substrate among the drift layer, and a maximum value of donor concentration of the lifetime control region is equal to or less than 1.0×10.sup.15/cm.sup.3.

A semiconductor device includes a first electrode and a second electrode. The first electrode is connected to a collector layer and a first portion on the collector layer side of a cathode layer. The second electrode is connected to a second portion of the cathode layer excluding the first portion. A work function of the first electrode is larger than a work function of the second electrode, and one of the first electrode and the second electrode and the semiconductor substrate sandwich another of the first electrode and the second electrode in a thickness direction of the semiconductor substrate.

An electrostatic discharge (ESD) protection device is provided. The ESD protection device includes a substrate, an active region, a first terminal region, and a second terminal region. The substrate includes dopants having a first dopant conductivity. The active region is arranged over the substrate and has an upper surface. The first terminal region and the second terminal region are arranged in the active region laterally spaced apart from each other. The first terminal region and the second terminal region each include a well region having dopants of the first dopant conductivity and a first doped region arranged in the well region. The first doped region includes dopants having a second dopant conductivity.

A flexible wire comprises a conductive core surrounded by one or more radial p-n diodes and alternating conductive and non-conductive bands along an outermost surface. Methods for producing the wire are also disclosed, as are textiles and other flexible materials comprising or consisting of such flexible wires.

The present disclosure relates generally to structures in semiconductor devices and methods of forming the same. More particularly, the present disclosure relates to high electron mobility transistor (HEMT) devices having a silicided polysilicon layer. The present disclosure may provide an active region above a substrate, source and drain electrodes in contact with the active region, a gate above the active region, the gate being laterally between the source and drain electrodes, a polysilicon layer above the substrate, and a silicide layer on the polysilicon layer. The active region includes at least two material layers with different band gaps. The polysilicon layer may be configured as an electronic fuse, a resistor, or a diode.

A method includes providing a first semiconductor layer at a frontside of a structure; implanting first dopants of a first conductivity-type into the first semiconductor layer, resulting in a doped layer in the first semiconductor layer; forming a stack of semiconductor layers over the first semiconductor layer; patterning the stack of semiconductor layers and the first semiconductor layer into fins; forming an isolation structure adjacent to a lower portion of the fins; etching the stack of semiconductor layers to form a source/drain trench over the first semiconductor layer; forming a source/drain feature in the source/drain trench, wherein the source/drain feature is doped with second dopants of a second conductivity-type opposite to the first conductivity-type; forming a contact hole at a backside of the structure, wherein the contact hole exposes the doped layer in the first semiconductor layer; and forming a first contact structure in the contact hole.

Disclosed herein are IC devices, packages, and device assemblies that include diodes arranged so that their first and second terminals may be contacted from the opposite faces of a support structure. Such diodes are referred to herein as “vertical diodes” to reflect the fact that the diode extends, in a vertical direction (i.e., in a direction perpendicular to the support structure), between the bottom and the top of support structures. Vertical diodes as described herein may introduce additional degrees of freedom in diode choices in terms of, e.g., high-voltage handling, capacitance modulation, and speed.

A method for fabricating a low-gain avalanche diode (LGAD) device is provided. The method includes: forming a low-resistivity n-type semiconductor substrate in a first silicon wafer; forming a p-type gain layer in an upper surface of a high-resistivity p-type second silicon wafer; bonding the first and second wafers such that the upper surface of the second wafer proximate the gain layer contacts the semiconductor substrate in the first wafer to form a bonded wafer structure, whereby a back surface of the second wafer becomes an upper surface of the bonded wafer structure; forming a plurality of p-type electrodes in the upper surface of the bonded wafer structure; and forming a conductive layer on at least a portion of the respective p-type electrodes and on a back surface of the semiconductor substrate, the conductive layer providing electrical connection to the LGAD device.