A semiconductor device includes a semiconductor substrate, an element region including an active element formed at the semiconductor substrate, a channel stopper formed in an outer peripheral region of the semiconductor substrate, and an insulating film that covers a surface of the semiconductor substrate and that has a first contact hole by which the channel stopper is exposed. The semiconductor device further includes a first field plate, a second field plate, and an equipotential ring electrode. The first field plate is formed on the insulating film, and faces the semiconductor substrate between the channel stopper and the element region through the insulating film. The second field plate is embedded in the insulating film, and faces the semiconductor substrate between the first field plate and the channel stopper through the insulating film. The equipotential ring electrode is formed along an outer peripheral region of the semiconductor substrate. The equipotential ring electrode is connected to the channel stopper through the first contact hole, and is connected to the first field plate, and is connected to the second field plate through a second contact hole formed in the insulating film.

A method of manufacturing a semiconductor device having an insulated gate bipolar transistor portion and a freewheeling diode portion. The method includes introducing an impurity to a rear surface of a semiconductor substrate, performing first heat treating to activate the impurity to form a field stop layer, performing a first irradiation to irradiate light ions from the rear surface of semiconductor substrate to form, in the semiconductor substrate, a first low-lifetime region, performing a second irradiation to irradiate the light ions from the rear surface of the semiconductor substrate to form, in the field stop layer, a second low-lifetime region, and performing second heat treating to reduce a density of defects generated in the field stop layer when the second irradiation is performed. Each of the first and second low-lifetime regions has a carrier lifetime thereof shorter than that of any region of the semiconductor device other than the first and second low-lifetime regions.

A power semiconductor device has a semiconductor body configured to conduct a load current in parallel to an extension direction between first and second load terminals of the power semiconductor device. The semiconductor body includes a doped contact region electrically connected to the second load terminal, a doped drift region having a dopant concentration that is smaller than a dopant concentration of the contact region, and an epitaxially grown doped transition region separated from the second load terminal by the contact region and that couples the contact region to the drift region. An upper subregion of the transition region is in contact with the drift region, and a lower subregion of the transition region is in contact with the contact region. The transition region has a dopant concentration of at least 0.5*10.sup.15 cm.sup.−3 for at least 5% of the total extension of the transition region in the extension direction.

An embodiment of a semiconductor device includes forming an active region that extends vertically into the semiconductor material in which the semiconductor device is formed. The active region may include a P-N junction or alternately a gate or a channel region of an MOS transistor.

Techniques are provided herein to form a semiconductor diode device within an integrated circuit. In an example, a diode device includes separate fins or bodies of semiconductor material that are separated by an insulating barrier. One of the fins or bodies is doped with n-type dopants while the other fin or body is doped with p-type dopants. Each of the first and second fins or bodies includes an epitaxially grown region over it that includes the corresponding dopant type with a higher dopant concentration. Additionally, each of the first and second fins or bodies includes another epitaxially grown region on the backside (e.g., under the fins or bodies) of the corresponding dopant type with a lower dopant concentration compared to the epitaxial regions on the opposite side of the fins or bodies. An undoped or lightly doped layer may also be formed between the epitaxially grown regions on the backside.

Embodiments are directed to a method for forming a semiconductor structure by depositing a stack of alternating layers of two materials over a substrate and defining field-effect transistor and diode regions. The method further includes depositing a mask, where the mask covers only the field-effect transistor region while leaving the diode region uncovered. The method further includes doping the material in the diode region with a dopant, implanting epitaxial material with another dopant to form PN junctions, stripping the mask from the structure, forming a metal gate conductor over the field-effect transistor region, and depositing a metal over the substrate to create terminals.

The present invention generally relates to nanoscale wires and, in particular, to nanoscale wires with heterojunctions, such as tip-localized homo- or heterojunctions. In one aspect, the nanoscale wire may include a core, an inner shell surrounding the core, and an outer shell surrounding the inner shell. The outer shell may also contact the core, e.g., at an end portion of the nanoscale wire. In some cases, such nanoscale wires may be used as electrical devices. For example a p-n junction may be created where the inner shell is electrically insulating, and the core and the outer shell are p-doped and n-doped. Other aspects of the present invention generally relate to methods of making or using such nanoscale wires, devices, or kits including such nanoscale wires, or the like.

The embodiment relates to a light emitting device, a method of fabricating the same, a light emitting device package, and a lighting system. According to the embodiment, a light emitting device includes a light emitting structure including a first conductive semiconductor layer, an active layer, a second conductive semiconductor layer, a first electrode electrically connected with the first conductive semiconductor layer, a second electrode electrically connected with the second conductive semiconductor layer, an insulating member provided on the light emitting structure while exposing the first electrode and the second electrode, a third electrode provided on the first electrode, and a fourth electrode provided on the second electrode. The third electrode includes a first part of the third electrode directly making contact with the first electrode and a second part of the third electrode, which is provided on the first part of the third electrode and has a horizontal width wider than the first part of the third electrode, and the fourth electrode includes a first part of the fourth electrode directly making contact with the second electrode and a second part of the fourth electrode, which is provided on the first part of the fourth electrode and has a horizontal width wider than the first part of the fourth electrode. The light extraction efficiency and the heat radiation characteristic may be improved, and the reliability may be improved.

A gallium nitride power device, including: a gallium nitride substrate; cathodes; a plurality of gallium nitride protruding structures arranged on the gallium nitride substrate and between the cathodes, a groove is formed between adjacent gallium nitride protruding structures; an electron transport layer, covering a top portion and side surfaces of each of the gallium nitride protruding structures; a gallium nitride layer, arranged on the electron transport layer and filling each of the grooves; a plurality of second conductivity type regions, where each of the second conductivity type regions extends downward from a top portion of the gallium nitride layer into one of the grooves, and the top portion of each of the gallium nitride protruding structures is higher than a bottom portion of each of the second conductivity type regions; and an anode, arranged on the gallium nitride layer and the second conductivity type regions.

A semiconductor device a first semiconductor layer of a first conductivity type at a first main side of a semiconductor wafer and a second semiconductor layer of a second conductivity type at second main side. The second semiconductor layer forms a pn junction with the first semiconductor layer. A first electrode is in ohmic contact with the first semiconductor layer and a second electrode layer is in ohmic contact with the second semiconductor layer. A first semiconductor region of the first conductivity type completely embedded in the second semiconductor layer and a second semiconductor region of the first conductivity type completely embedded in the second semiconductor layer.