A semiconductor device includes: an interlayer insulating film covering: a cathode region and an anode region to form a pn junction with each other; a cathode electrode provided on the interlayer insulating film and connected to the cathode region through a first contact hole; and an anode electrode provided on the interlayer insulating film and connected to the anode region through a second contact hole. Among current paths in the cathode and anode regions, the current path in one of the cathode and anode regions that has a larger sheet resistance is shorter than the other current path, the current path in the cathode region extending from an interface of the pn junction to an end of the first contact hole closest to the interface, the current path in the anode region extending from the interface to an end of the second contact hole closest to the interface.

A method of forming a vertical finFET and vertical diode device on the same substrate, including forming a channel layer stack on a heavily doped layer; forming fin trenches in the channel layer stack; oxidizing at least a portion of the channel layer stack inside the fin trenches to form a dummy layer liner; forming a vertical fin in the fin trenches with the dummy layer liner; forming diode trenches in the channel layer stack; oxidizing at least a portion of the channel layer stack inside the diode trenches to form a dummy layer liner; forming a first semiconductor segment in a lower portion of the diode trenches with the dummy layer liner; and forming a second semiconductor segment in an upper portion of the diode trenches with the first semiconductor segment, where the second semiconductor segment is formed on the first semiconductor segment to form a p-n junction.

A super junction (SJ) device may include one or more charge balance (CB) layers. Each CB layer may include an epitaxial (epi) layer having a first conductivity type and a plurality of charge balance (CB) regions having a second conductivity type. Additionally, the SJ device may include a connection region having the second conductivity type that extends from a region disposed in a top surface of a device layer of the SJ device to one or more of the CB regions. The connection region may enable carriers to flow directly from the region to the one or more CB regions, which may decrease switching losses of the SJ device.

At edge termination region, a trench is disposed near an interface of an active region. Inside the trench, an embedded insulating film is embedded, and inside the embedded insulating film, a FP long in a direction of depth is disposed. The FP curves outwardly away from an inner side wall of the trench as a depth from a base front surface increases. At least near a bottom end of the FP, a distance between the FP and the inner side wall of the trench is greater than a width of the groove. The FP is connected to a front surface electrode that extends on the embedded insulating film. As a result, breakdown voltage may be enhanced, adverse effects of the surface charge may be reduced, and chip size may be further reduced.

At edge termination region, a trench is disposed near an interface of an active region. Inside the trench, an embedded insulating film is embedded, and inside the embedded insulating film, a FP long in a direction of depth is disposed. The FP curves outwardly away from an inner sidewall of the trench as a depth from a base front surface increases. At least near a bottom end of the FP, a distance between the FP and the inner sidewall of trench is greater than a width of the groove. The FP is connected to a front surface electrode that extends on the embedded insulating film. As a result, breakdown voltage can be enhanced, adverse effects of the surface charge can be reduced, and chip size can be further reduced.

According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a first semiconductor region, a second semiconductor region, a third semiconductor region, and a fourth semiconductor region. The first semiconductor region is provided between the first and second electrodes. The second semiconductor region is provided between the first semiconductor region and the second electrode. The third semiconductor region is provided between the first semiconductor region and the second electrode, is provided beside the second semiconductor region in a second direction crossing a first direction from the first electrode toward the second electrode, and a portion of the first semiconductor region is positioned between the third and second semiconductor regions. The fourth semiconductor region is provided between the portion of the first semiconductor region and the second electrode and has a greater impurity concentration than the second and third semiconductor regions.

An integrated diode (100) comprising a substrate (102); a Schottky cell (104) on the substrate (102); a heterojunction cell (106) on the substrate (102); a common anode contact (108) for both the Schottky cell (104) and the heterojunction cell (106); and a common cathode contact (110) for both the Schottky cell (104) and the heterojunction cell (106).

A method of forming a semiconductor device may include providing a semiconductor substrate, the semiconductor substrate comprising an inner region of a first polarity, and a surface layer, disposed on the inner region, wherein the surface layer comprises a second polarity, opposite the first polarity. The method may further include removing a surface portion of the semiconductor substrate using a saw, wherein a trench region is formed within the semiconductor substrate, and cleaning the trench region using a chemical process, wherein at least one mesa structure is formed within the semiconductor substrate.

A method for forming a semiconductor device includes incorporating first dopant atoms of a first conductivity type into a semiconductor substrate to form a first doping region of the first conductivity type. Further, the method includes forming an epitaxial semiconductor layer on the semiconductor substrate and incorporating second dopant atoms of a second conductivity type before or after forming the epitaxial semiconductor layer to form a second doping region including the second conductivity type adjacent to the first doping region so that a pn-junction is located between the first doping region and the second doping region. The pn-junction is located in a vertical distance of less than 5 μm to an interface between the semiconductor substrate and the epitaxial semiconductor layer. Additionally, the method includes thinning the semiconductor substrate based on a self-aligned thinning process. The self-aligned thinning process is self-controlled based on the location of the pn-junction.

A termination structure for a nitride-based Schottky diode includes a guard ring formed by an epitaxially grown P-type nitride-based compound semiconductor layer and dielectric field plates formed on the guard ring. The termination structure is formed at the edge of the anode electrode of the Schottky diode and has the effect of reducing electric field crowding at the anode electrode edge, especially when the Schottky diode is reverse biased. In one embodiment, the P-type epitaxial layer includes a step recess to further enhance the field spreading effect of the termination structure.