Disclosed are systems, devices and methods for utilizing an interconnect conductor to inhibit or reduce the likelihood of de-lamination of a passivation layer of an integrated circuit die. In some implementations, a metal layer in ohmic contact with an intrinsic region of a semiconductor substrate can be partially covered by a passivation layer such as a dielectric layer. An interconnect conductor electrically connected to the metal layer can include an extension that covers an edge of the passivation layer to thereby inhibit the edge from lifting up. In some implementations, the metal layer in combination with a contact pad also in ohmic contact with the intrinsic region can yield a conduction path through the intrinsic region during an electrostatic discharge (ESD) event. In such a configuration, the interconnect conductor can route the ESD charge to a ground.

An integrated diode (100) comprising a substrate (102); a Schottky cell (104) on the substrate (102); a heterojunction cell (106) on the substrate (102); a common anode contact (108) for both the Schottky cell (104) and the heterojunction cell (106); and a common cathode contact (110) for both the Schottky cell (104) and the heterojunction cell (106).

The semiconductor device of the present invention includes a first conductivity type semiconductor layer made of a wide bandgap semiconductor and a Schottky electrode formed to come into contact with a surface of the semiconductor layer, and has a threshold voltage V.sub.th of 0.3 V to 0.7 V and a leakage current J.sub.r of 1×10.sup.−9 A/cm.sup.2 to 1×10.sup.−4 A/cm.sup.2 in a rated voltage V.sub.R.

A termination structure for a nitride-based Schottky diode includes a guard ring formed by an epitaxially grown P-type nitride-based compound semiconductor layer and dielectric field plates formed on the guard ring. The termination structure is formed at the edge of the anode electrode of the Schottky diode and has the effect of reducing electric field crowding at the anode electrode edge, especially when the Schottky diode is reverse biased. In one embodiment, the P-type epitaxial layer includes a step recess to further enhance the field spreading effect of the termination structure.

A semiconductor device includes: a first conductive type semiconductor device; a first conductive type drift region formed by epitaxial growth on the semiconductor substrate; a plurality of first conductive type vertical implantation regions formed by multistage ion implantation in the drift region, the vertical implantation regions having a prescribed vertical implantation width and a prescribed drift region width; an anode electrode disposed on the front surface of the drift region opposite to the semiconductor substrate, the anode electrode being in Schottky contact with the drift region and in ohmic contact with the first conductive type vertical implantation regions; and a cathode electrode disposed on the rear surface of the semiconductor substrate opposite to the drift region, the cathode electrode being in ohmic contact with the semiconductor substrate.

A power device includes a substrate, a drift layer disposed on the substrate, a terminal region and an active region disposed in the drift layer, an electrode layer disposed on the active region, a Schottky contact layer disposed between the electrode layer and the active region, a passivation layer disposed on the drift layer, and an isolation layer disposed between the passivation layer and the electrode layer so that the passivation layer and the electrode layer are at least partially separated from each other. The isolation layer, the electrode layer, and the passivation layer each respectively has a thermal expansion coefficient a, b, c, and a>b>c.

A trench MOS Schottky diode includes a first semiconductor layer including a Ga.sub.2O.sub.3-based single crystal, a second semiconductor layer that is a layer stacked on the first semiconductor layer, includes a Ga.sub.2O.sub.3-based single crystal, and includes a trench opened on a surface thereof opposite to the first semiconductor layer, an anode electrode formed on the surface of the second semiconductor layer, a cathode electrode formed on a surface of the first semiconductor layer, an insulating film covering the inner surface of the trench of the second semiconductor layer, and a trench electrode that is buried in the trench of the second semiconductor layer so as to be covered with the insulating film and is in contact with the anode electrode. The second semiconductor layer includes an insulating dry-etching-damaged layer with a thickness of not more than 0.8 μm in a region including the inner surface of the trench.

In one embodiment, a breakdown voltage blocking device can include an epitaxial region located above a substrate and a plurality of source trenches formed in the epitaxial region. Each source trench can include a dielectric layer surrounding a conductive region. The breakdown voltage blocking device can also include a contact region located in an upper surface of the epitaxial region along with a gate trench formed in the epitaxial region. The gate trench can include a dielectric layer that lines the sidewalls and bottom of the gate trench and a conductive region located between the dielectric layer. The breakdown voltage blocking device can include source metal located above the plurality of source trenches and the contact region. The breakdown voltage blocking device can include gate metal located above the gate trench.

Provided is a semiconductor device and a method for forming the same. The device has a substrate including one and another surfaces. A first semiconductor region of a first conductivity type is formed in the substrate. A second conductivity type, second semiconductor region is provided in a first surface layer, that includes the one surface, of the substrate. A first electrode is in contact with the second semiconductor region to form a junction therebetween. A first conductivity type, third semiconductor region is provided in a second surface layer, that includes the another surface, of the substrate. The third semiconductor region has a higher impurity concentration than the first semiconductor region. A fourth semiconductor region of the second conductivity type is provided in the first semiconductor region at a location deeper than the third semiconductor region from the another surface. A second electrode is in contact with the third semiconductor region.

Under one aspect, a power Schottky diode includes a cathode; a semiconductor disposed over the cathode, the semiconductor including at least a first region and a second region, the second region defining a guard ring; an anode disposed over the first region and at least a portion of the guard ring, the anode including a metal, a junction between the anode and the first region defining a Schottky barrier; and an oxide disposed over the guard ring. Additionally, the power Schottky diode can include a resistive material disposed over at least a portion of the guard ring and at least a portion of the oxide. The resistive material can inhibit a flow of holes from the guard ring to the anode following a heavy ion strike to the guard ring. The anode further can be disposed over at least a portion of, or the entirety of, the resistive material.