A capacitor structure is described. A capacitor structure including a substrate and at least one device formed on the substrate. The device including first and second sections. Each of the first and second sections including a plurality of source/drain regions formed in the substrate and a plurality of gates formed above the substrate such that each of the plurality of gates is formed between each pair of source/drain regions to form a section channel between each pair of source/drain regions. The plurality of gates of the first and second sections are coupled with each other.

Certain aspects of the present disclosure provide a semiconductor variable capacitor. The semiconductor variable capacitor generally includes a semiconductor region, an insulative layer disposed above the semiconductor region, and a first non-insulative region disposed above the insulative layer. In certain aspects, a second non-insulative region is disposed adjacent to the semiconductor region, and a control region is disposed adjacent to the semiconductor region such that a capacitance between the first non-insulative region and the second non-insulative region is configured to be adjusted by varying a control voltage applied to the control region. In certain aspects, the first non-insulative region is disposed above a first portion of the semiconductor region and a second portion of the semiconductor region, and the first portion and the second portion of the semiconductor region are disposed adjacent to a first side and a second side, respectively, of the control region or the second non-insulative region.

Certain aspects of the present disclosure provide a semiconductor variable capacitor. The semiconductor variable capacitor generally includes a first non-insulative region disposed above a semiconductor region, and a second non-insulative region disposed adjacent to the semiconductor region. In certain aspects, the semiconductor variable capacitor also includes a first silicide layer disposed above the second non-insulative region, wherein the first silicide layer overlaps at least a portion of the semiconductor region. In certain aspects, a control region may be disposed adjacent to the semiconductor region such that a capacitance between the first non-insulative region and the second non-insulative region is configured to be adjusted by varying a control voltage applied to the control region.

A chip capacitor according to the present invention includes a substrate, a pair of external electrodes formed on the substrate, a capacitor element connected between the pair of external electrodes, and a bidirectional diode connected between the pair of external electrodes and in parallel to the capacitor element. Also, a circuit assembly according to the present invention includes the chip capacitor according to the present invention and a mounting substrate having lands, soldered to the external electrodes, on a mounting surface facing a front surface of the substrate.

Certain aspects of the present disclosure provide a semiconductor capacitor. The semiconductor capacitor generally includes a first non-insulative region disposed above an insulative layer, an insulative region, and a second non-insulative region disposed adjacent to the insulative region, wherein the insulative layer is disposed above the second non-insulative region and the insulative region. In some cases, at least a portion of the insulative region is disposed above one or more portions of the second non-insulative region.

Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a substrate with an active layer overlying a buried insulator layer that in turn overlies a handle layer, where the active layer includes a first active well. A first source, a first drain, and a first channel are defined within the first active well, where the first channel is between the first source and the first drain. A first gate dielectric directly overlies the first channel, and a first gate directly overlies the first gate dielectric, where a first capacitor includes the first source, the first drain, the first channel, the first gate dielectric, and the first gate. A first handle well is defined within the handle layer directly underlying the first channel and the buried insulator layer.

The present disclosure provides a method of forming a nanolaminate structure. First, a pre-treatment is performed on a semiconductor substrate, in which the semiconductor substrate includes SiGe. Then, a first metal oxide layer is formed on the semiconductor substrate. Then, at least one second metal oxide layer and at least one third metal oxide layer are alternately stacked on the first metal oxide layer, thereby forming a nanolaminate structure. And, a conductive gate layer is formed on the nanolaminate structure.

Embodiments are provided herein for low loss coupling capacitor structures. The embodiments include a n-type varactor (NVAR) configuration and p-type varactor (PVAR) configuration. The structure in the NVAR configuration comprises a p-doped semiconductor substrate (Psub), a deep n-doped semiconductor well (DNW) in the Psub, and a p-doped semiconductor well (P well) in the DNW. The circuit structure further comprises a source terminal of a p-doped semiconductor material within P well, and a drain terminal of the p-doped semiconductor material within the P well. Additionally, the circuit structure comprises an insulated gate on the surface of the P well, a metal pattern comprising a plurality of layers of metal lines, and a plurality of vias through the metal lines. The vias are contacts connecting the metal lines to the gate, the source terminal, and the drain terminal.

Certain aspects of the present disclosure provide a semiconductor variable capacitor based on a buried oxide process. The semiconductor variable capacitor generally includes a first conductive pad coupled to a first non-insulative region and a second conductive pad coupled to a second non-insulative region. The second non-insulative region may be coupled to a semiconductor region. The capacitor may also include a first control region coupled to the first semiconductor region such that a capacitance between the first conductive pad and the second conductive pad is configured to be adjusted by varying a control voltage applied to the first control region. The capacitor also includes an insulator region disposed below the semiconductor region, wherein at least a portion of the first non-insulative region is separated from the second non-insulative region by the insulator region such that the first conductive pad is electrically isolated from the second conductive pad.

A method of manufacturing a capacitor structure is provided, including the following steps. A substrate is provided. A first doped silicon material layer is formed on the substrate. A surface flattening process is performed on the first doped silicon material layer through a plasma treatment. An insulating material layer is formed on the first doped silicon material layer after the surface flattening process is performed. A second doped silicon material layer is formed on the insulating material layer. The first doped silicon material layer is patterned into a first electrode. The insulating material layer is patterned into an insulating layer. The second doped silicon material layer is patterned into a second electrode. The method of manufacturing the capacitor structure may be used to produce a capacitor with better reliability and may improve capacitance density.