A memory cell based upon thyristors for an SRAM integrated circuit can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM cells. Special circuitry provides lowered power consumption during standby.

The present disclosure relates to a Silicon Controlled Rectifier (SCR) in non-planar technology to provide a robust ESD protection in System on Chip employing non-planar technologies. The disclosed SCR incorporates wire or fin shaped nanostructures extending from p-type tap to cathode, from the cathode to anode, and from the anode to n-type tap to provide parallel trigger paths to prevent problem of current crowding at the base emitter junction that limits efficient turn-on in conventional SCRs. The proposed structure helps in offering lower trigger and holding voltage, and therefore very high failure currents. The disclosed SCR has sub-3V trigger and holding voltage to provide an efficient and robust ESD protection in SOCs. The proposed device also offers three times better ESD robustness per unit area. Further the proposed SCR has no added capacitive loading and is compatible with standard process flow and design rules.

Various embodiments include fin-type field effect transistor (FinFET) structures. In some cases, a FinFET structure includes: a substrate; a silicon-controlled rectifier (SCR) over the substrate, the SCR including: a p-well region and an adjacent n-well region over the substrate; and a negatively charged fin over the p-well region; and a Schottky diode electrically coupled with the SCR, the Schottky diode spanning between the p-well region and the n-well region, the Schottky diode for controlling electrostatic discharge (ESD) across the negatively charged fin and the n-well region.

A memory circuit with thyristor includes a plurality of memory cells. Each memory cell of the plurality of memory cells includes an access transistor and a thyristor. The thyristor is coupled to the access transistor. At least one of a gate of the access transistor and a gate of the thyristor has a fin structure.

A power transmission device includes a power transmission coil, a power-transmission resonance capacitor that forms, together with the power transmission coil, a power-transmission resonance mechanism, and a power transmission circuit electrically connected to the power-transmission resonance mechanism that intermittently applies a direct-current input voltage to the power-transmission resonance mechanism and causes the power transmission coil to generate an alternating-current voltage. The power transmission circuit includes a control circuit section including an oscillator, and a power circuit section formed of an integrated circuit sealed in a small-sized package with a plurality of terminals. The integrated circuit is electrically and directly connected to the power-transmission resonance mechanism. The control circuit section oscillates at a predetermined frequency and outputs a driving signal which is input to the power circuit section. The power circuit section intermittently applies a direct-current voltage to the power-transmission resonance mechanism using a transistor in the integrated circuit.

Memory arrays of vertical thyristor memory cells with SiGe base layers are described. The composition of the SiGe can be constant or varied depending upon the desired characteristics of the memory cells. The memory cells allow a compact structure with desirable low voltage operations.

Provided is an electrostatic protection circuit that has little leakage current under normal operation and allows a trigger voltage to be set comparatively freely, without requiring a special process step. This electrostatic protection circuit is provided with a series circuit including a transistor, a predetermined number of diodes and an impedance element that are connected in series between the first node and the second node, and a discharge circuit configured to send current from the first node to the second node following an increase in a potential difference that occurs between both ends of the impedance element, when the first node reaches a higher potential than the second node and current flows through the series circuit. The predetermined number of diodes are connected between the source and the back gate of the transistor.

Provided is a small-area one-time programmable semiconductor memory device that uses a PNPN structure, which is parasitically generated in a CMOS process. An N-type region provided in a location other than both ends or a P-type region provided in a location other than both the ends is put into a floating state so that PNPN current flows, and a thermal breakdown of a resistor caused by this current is used as a memory element.

An electronic device can include a bidirectional HEMT. In an aspect, the electronic device can include a pair of switch gate and blocking gate electrodes, wherein the switch gate electrodes are not electrically connected to the blocking gate electrodes, and the first blocking, first switch, second blocking, and second switch gate electrodes are on the same die. In another aspect, the electronic device can include shielding structures having different numbers of laterally extending portions. In a further aspect, the electronic device can include a gate electrode and a shielding structure, wherein a portion of the shielding structure defines an opening overlying the gate electrode.