A light-emitting component includes a light-emitting element, a driving thyristor, and a light-absorbing layer. The light-emitting element emits light of a predetermined wavelength. The driving thyristor causes the light-emitting element to emit light or causes an amount of light emitted by the light-emitting element to increase, upon entering an on-state. The light-absorbing layer is disposed between the light-emitting element and the driving thyristor such that the light-emitting element and the driving thyristor are stacked, and absorbs light emitted by the driving thyristor.

An insulated gate turn-off (IGTO) device, formed as a die, has a layered structure including a p+ layer (e.g., a substrate), an n− drift layer, a p-well, trenched insulated gates formed in the p-well, and n+ regions between at least some of the gates, so that vertical npn and pnp transistors are formed. A cathode electrode is on top, and an anode electrode is on the bottom of the substrate. The device is formed of a matrix of cells. To turn the device on, a positive voltage is applied to the gates, referenced to the cathode electrode. To direct high energy electrons away from a gate oxide layer on the sidewalls of the trenches, boron is implanted between the trenches so p+ regions are formed in the mesas of the less-doped p-well. The p+ regions break down during an over-voltage event before the p-well breaks down in the mesas.

A lateral insulated gate turn-off device includes an n-drift layer, a p-well formed in the n− drift layer, a shallow n+ type region formed in the well, a shallow p+ type region formed in the well, a cathode electrode shorting the n+ type region to the p+ type region, a trenched first gate extending through the n+ type region and into the well, a p+ type anode region laterally spaced from the well, an anode electrode electrically contacting the p+ type anode region, and a trenched second gate extending from the p+ type anode region into the n-drift layer. For turning the device on, a positive voltage is applied to the first gate the reduce the base width of the npn transistor, and a negative voltage is applied to the second gate to effectively extend the p+ emitter of the pnp transistor further into the n-drift layer to improve performance.

A lateral insulated gate turn-off device includes an n-drift layer, a p-well formed in the n− drift layer, a shallow n+ type region formed in the well, a shallow p+ type region formed in the well, a cathode electrode shorting the n+ type region to the p+ type region, a trenched first gate extending through the n+ type region and into the well, a p+ type anode region laterally spaced from the well, an anode electrode electrically contacting the p+ type anode region, and a trenched second gate extending from the p+ type anode region into the n-drift layer. For turning the device on, a positive voltage is applied to the first gate the reduce the base width of the npn transistor, and a negative voltage is applied to the second gate to effectively extend the p+ emitter of the pnp transistor further into the n-drift layer to improve performance.

A method of manufacturing a semiconductor integrated circuit includes forming a body region having a second conductivity type in an upper portion of a support layer having a first conductivity type and forming a well region having a second conductivity type in an upper portion of the support layer. An output side buried layer is formed inside the body region and a circuit side buried layer is formed inside the well region. A trench is dug to penetrate through the body region and a control electrode structure is buried in the gate trench. First and second terminal regions are formed on the well region and an output terminal region is formed on the body region. An output stage element having the output terminal region is controlled by a circuit element including the first and second terminal regions.

Insulated gate semiconductor device includes drift layer of first conductivity type; first base region of second conductivity type on the drift layer; carrier-supply region of the first conductivity type on the first base region and having higher impurity concentration than the drift layer; a first contact region of the second conductivity type on the first base region and having higher impurity concentration than the first base regions; cell-pillars each having polygonal-shape, arranged in a lattice-pattern, sidewalls of the cell-pillars are defined by trenches penetrating the carrier-supply region, the first contact region, and the first base region; and insulated-gate electrode-structures in the trenches. A first pillar selected from the cell-pillars includes the carrier-supply region, the first contact region and the first base region, and the first contact regions are in contact with a limited portion of an outer periphery of a first pillar at a top surface of the first pillar.

Methods, apparatus, and processor-readable storage media for automatically limiting power consumption by devices using infrared or radio communications are provided herein. An example computer-implemented method includes detecting, via at least one photodiode of an emitting sensor, one or more signals output by a user device within a predetermined proximity; automatically transitioning, via utilizing at least one transistor connected to the photodiode, and in response to detecting the one or more signals, the emitting sensor from a first power-consumption state to a second power-consumption state; transmitting one or more signals in response to transitioning from the first power-consumption state to the second power-consumption state; and subsequent to transmitting, automatically transitioning, via utilizing the at least one transistor, the emitting sensor from the second power-consumption state to the first power-consumption state after a predetermined amount of time has elapsed during which no signals were detected.

Methods, apparatus, and processor-readable storage media for automatically limiting power consumption by devices using infrared or radio communications are provided herein. An example computer-implemented method includes detecting, via at least one photodiode of an emitting sensor, one or more signals output by a user device within a predetermined proximity; automatically transitioning, via utilizing at least one transistor connected to the photodiode, and in response to detecting the one or more signals, the emitting sensor from a first power-consumption state to a second power-consumption state; transmitting one or more signals in response to transitioning from the first power-consumption state to the second power-consumption state; and subsequent to transmitting, automatically transitioning, via utilizing the at least one transistor, the emitting sensor from the second power-consumption state to the first power-consumption state after a predetermined amount of time has elapsed during which no signals were detected.

The subject matter disclosed herein relates to semiconductor power devices, such as silicon carbide (SiC) power devices. In particular, the subject matter disclosed herein relates to shielding regions in the form of body region extensions for that reduce the electric field present between the well regions of neighboring device cells of a semiconductor device under reverse bias. The disclosed body region extensions have the same conductivity-type as the body region and extend outwardly from the body region and into the JFET region of a first device cell such that a distance between the body region extension and a region of a neighboring device cell having the same conductivity type is less than or equal to the parallel JFET width. The disclosed shielding regions enable superior performance relative to a conventional stripe device of comparable dimensions, while still providing similar reliability (e.g., long-term, high-temperature stability at reverse bias).

A semiconductor integrated circuit includes: an n.sup.-type support layer; a p-type well region provided in an upper portion of the support layer; a p.sup.+-type circuit side buried layer provided inside the well region; an n.sup.+-type first and second terminal regions provided in an upper portion of the well region and above the circuit side buried layer; a p-type body region provided in an upper portion of the support layer; a control electrode structure provided in a gate trench; a p.sup.+-type output side buried layer provided inside the body region so as to be in contact with the control electrode structure; and an n.sup.+-type output terminal region provided in an upper portion of the body region and above the output side buried layer, wherein an output stage element having the output terminal region is controlled by a circuit element including the first and second terminal regions.