Photovoltaic devices such as solar cells having one or more field-effect hole or electron inversion/accumulation layers as contact regions are configured such that the electric field required for charge inversion and/or accumulation is provided by the output voltage of the photovoltaic device or that of an integrated solar cell unit. In some embodiments, a power source may be connected between a gate electrode and a contact region on the opposite side of photovoltaic device. In other embodiments, the photovoltaic device or integrated unit is self-powering.

A microfluidic system includes a liquid drop accommodation space, an array of photosensitivity detection circuits and an array of driving circuits between an upper substrate and a lower substrate. Each photosensitivity detection circuit includes a photosensitive transistor and a first gating transistor. The photosensitive transistor has a gate electrode coupled to a first scan signal line, a source electrode coupled to a first power supply voltage signal line, and a drain electrode coupled to a source electrode of the first gating transistor. The first gating transistor has a gate electrode coupled to a second scan signal line, and a drain electrode coupled to a read signal line. Each driving circuit includes a driving transistor and a driving electrode. The driving transistor has a gate electrode coupled to a third scan signal line, a source electrode coupled to a data signal line, and a drain electrode coupled to the driving electrode.

Photovoltaic devices such as solar cells having one or more field-effect hole or electron inversion/accumulation layers as contact regions are configured such that the electric field required for charge inversion and/or accumulation is provided by the output voltage of the photovoltaic device or that of an integrated solar cell unit. In some embodiments, a power source may be connected between a gate electrode and a contact region on the opposite side of photovoltaic device. In other embodiments, the photovoltaic device or integrated unit is self-powering.

A two-terminal photon-effect transistor (PET) is described that simplifies the photo sensing pixel by combing photodiode and field effect transistor dual functions into one simple but effective unit. Photons excite electrons from the valance band of semiconducting material as the electrode-free gate to modulate resistivity between source and drain, which directly results in current amplification of photo signal without traditional photo-electrical conversion and electrical amplification dual processes. PET possesses significance in both structural simplification and functional enhancement. As an implementing example of PET, a nanowire camera (NC) with large sensing area and extremely high resolution is fabricated by integrating millions of vertically aligned nanowire arrays in-between of orthogonal top and bottom nano-stripe electrodes. Each nanowire works as independent three-dimensional (3D) PET pixel, enabling the NC an ultra-high resolution and much simplified architecture. NC has pixel size of 50 nm which is two orders higher than existing CCD and CMOS image sensors.

An optical sensor comprises a first and a second photodiode. Each photodiode comprises a respective light sensitive area. The second photodiode further comprises a wavelength-selective absorption layer arranged to selectively attenuate incident light before the light enters the light sensitive area of the second photodiode. The wavelength-selective absorption layer characterized by a low optical absorption in a wavelength range of 300 to 1100 nm and a high optical absorption in a wavelength range of 200 to 275 nm. The photodiodes are configured to generate respective electrical currents in response to incident light, and the optical sensor is configured to determine a light level based on a discrepancy between the electrical current generated by the first photodiode and the electrical current generated by the second photodiode.

An optical UV sensor comprises: a first photodiode sensitive to light in a first wavelength range and to light in a second wavelength range in the UV spectrum, wherein the second wavelength range comprises longer wavelengths than the first wavelength range, and wherein the first photodiode is configured to output a first signal in response to incident light; a second photodiode sensitive to light in the second wavelength range and comprising an absorption layer having an optical thickness in the range of 10 nm to 250 nm to absorb light in the first wavelength range, while being substantially transparent to light in the second wavelength range, wherein the second photodiode is configured to output a second signal in response to incident light; wherein the optical sensor is configured to output a difference between the first signal and the second signal.

A method of forming a light sensitive semiconductor structure is provided. The method includes providing a semiconductor wafer comprising a semiconductor layer comprising a light sensitive region, providing a gate structure comprising an insulation layer on said semiconductor layer and a polysilicon layer on said insulation layer, providing a contact stop layer on said gate structure, wherein said contact stop layer covers said light sensitive region, providing an etch mask, etching said contact stop layer using said etch mask to form said opening, etching said polysilicon layer using said etch mask, and providing a plurality of metal layers comprising a first metal layer electrically connected to said semiconductor layer and a plurality of dielectric layers between metal layers of said plurality of metal layers.

A ring-type FET may include a silicon base, a source formed on a portion of the silicon base through doping, a channel formed to encompass the source on a plane, a drain formed outside the channel, a dielectric layer formed on the source, the channel and the drain, and a gate provided on the dielectric layer, wherein a center of the source is spaced apart from a center of the channel, and the gate is formed of a metal material, disposed above the channel and configured to cover an upper face of the channel and overlap a portion of the source and a portion of the drain.

A ring-type FET may include a silicon base, a source formed on a portion of the silicon base through doping, a channel formed to encompass the source on a plane, a drain formed outside the channel, a dielectric layer formed on the source, the channel and the drain, and a gate provided on the dielectric layer, wherein a center of the source is spaced apart from a center of the channel, and the gate is formed of a metal material, disposed above the channel and configured to cover an upper face of the channel and overlap a portion of the source and a portion of the drain.