Apparatuses and methods are disclosed herein for the formation of low capacitance through substrate via structures. An example apparatus includes an opening formed in a substrate, wherein the opening has at least one sidewall, a first dielectric at least formed on the sidewall of the opening, a first conductor at least formed on the first dielectric, a second dielectric at least formed on the first conductor, and a second conductor at least formed on a sidewall of the second dielectric.

The present disclosure relates to an interposer. The interposer includes: a support body formed of a ceramic material, a connection electrode configured to the top surface and bottom surface of the support body, and a shielding member disposed at an outer surface of the support body. At least a part of the support body is disposed along the edge of a substrate, and electrically connects the substrate and a substrate. The interposer is formed of a ceramic material and thus make it possible to implement a fine pattern, to improve dimensional stability by preventing the bending deformation of ceramic green sheets, and to raise the reliability of signal transmission. Therefore, the interposer can contribute to implementing high performance of an electronic device and reducing the size of the electronic device.

An electronic device includes a rectangular ceramic package structure having opposite first and second sides, an interior cavity that extends to an opening in the second side, opposite third and fourth sides spaced along a first direction, opposite fifth and sixth sides spaced along an orthogonal second direction, and non-conductive indents extending into the third and fourth sides. The device also includes a semiconductor die in the cavity, a lid that covers the opening and seals the cavity, a conductive terminal having a planar side exposed along the first side that is electrically coupled to a circuit of the semiconductor die and extends to a first one of the non-conductive indents, and conductive pins spaced apart from the conductive terminal and extending outward from the first side of the ceramic package structure along a third direction.

An apparatus includes a printed circuit board (PCB), a solder pad, a signal via, a plurality of metalized vias, and a waveguide. The PCB has a first surface opposite a second surface and includes a first metal layer, a second metal layer having a waveguide opening, and a PCB channel region from the waveguide opening in the second metal layer to the second surface. The solder pad is positioned on the first surface of the PCB over the channel region, and the signal via is coupled to the solder pad and a via pad in the second metal layer within the waveguide opening. The plurality of metalized vias extend from the first surface to the second surface of the PCB and form a boundary around the channel region. The waveguide is affixed to the waveguide opening in the second metal layer.

A package comprising an integrated device and a substrate. The integrated device is coupled to the substrate. The substrate includes a core layer, at least one first dielectric layer coupled to a first surface of the core layer, and at least one second dielectric layer coupled to a second surface of the core layer. The substrate includes a match structure located in the core layer. The match structure includes at least one first match interconnect extending vertically and horizontally in the match structure. The match structure also includes at least one second match interconnect extending vertically in the match structure. The at least one first match interconnect and the at least one second match interconnect are configured for skew matching.

Provided is an electronic assembly including (a) an interconnect carrier having an electrically insulating core and at least two electrically conducting layers formed at the electrically insulating core; (b) a first integrated circuit chip mounted at a first side of the interconnect carrier; (c) a second integrated circuit chip mounted at a second side of the interconnect carrier opposite to the first side; and (d) an interconnection structure electrically connecting the first integrated circuit chip with the second integrated circuit chip. The electric interconnection structure extends around the insulating core and includes at least one electric conductor path which is designed in such a manner that an impedance match between the first integrated circuit chip and the second integrated circuit chip is provided. Further, there is provided an electronic system comprising such an electronic assembly.

Embodiments of the invention include a microelectronic device that includes an overmolded component having a first die with a silicon based substrate. A second die is coupled to the first die with the second die being formed with compound semiconductor materials in a different substrate. A substrate is coupled to the first die. The substrate includes an antenna unit for transmitting and receiving communications at a frequency of approximately 4 GHz or higher.

To improve signal transmission characteristics of a high frequency signal of 80 GHz or higher. A semiconductor device includes a wiring board having a structure in which a signal via structure and a grounding via structure have mutually overlapping portions in plan view.

A method for use with multiple chips, each respectively having a bonding surface including electrical contacts and a surface on a side opposite the bonding surface involves bringing a hardenable material located on a body into contact with the multiple chips, hardening the hardenable material so as to constrain at least a portion of each of the multiple chips, moving the multiple chips from a first location to a second location, applying a force to the body such that the hardened, hardenable material will uniformly transfer a vertical force, applied to the body, to the chips so as to bring, under pressure, a bonding surface of each individual chip into contact with a bonding surface of an element to which the individual chips will be bonded, at the second location, without causing damage to the individual chips, element, or bonding surface.

Methods for forming via last through-vias. A method includes providing an active device wafer having a front side including conductive interconnect material disposed in dielectric layers and having an opposing back side; providing a carrier wafer having through vias filled with an oxide extending from a first surface of the carrier wafer to a second surface of the carrier wafer; bonding the front side of the active device wafer to the second surface of the carrier wafer; etching the oxide in the through vias in the carrier wafer to form through oxide vias; and depositing conductor material into the through oxide vias to form conductors that extend to the active carrier wafer and make electrical contact to the conductive interconnect material. An apparatus includes a carrier wafer with through oxide vias extending through the carrier wafer to an active device wafer bonded to the carrier wafer.