A semiconductor package includes a first semiconductor device, a second semiconductor device vertically positioned above the first semiconductor device, and a ground shielded transmission path. The ground shielded transmission path couples the first semiconductor device to the second semiconductor device. The ground shielded transmission path includes a first signal path extending longitudinally between a first end and a second end. The first signal path includes a conductive material. A first insulating layer is disposed over the signal path longitudinally between the first end and the second end. The first insulating layer includes an electrically insulating material. A ground shielding layer is disposed over the insulating material longitudinally between the first end and the second end of the signal path. The ground shielding layer includes a conductive material coupled to ground. The ground shielding layer drives radiation signals received therein to ground to prevent induced noise in the first signal path.

Embodiments of an embedded mm-wave radio integrated circuit into a substrate of a phased array module are disclosed. In some embodiments, the phased array module includes a first set of substrate layers made of a first material. The mm-wave radio integrated circuit may be embedded in the first set of substrate layers. A second set of substrate layers may be coupled to the first set of substrate layers. The second set of substrate layers may be made of a second material that has a lower electrical loss than the first material. The second set of substrate layers may include a plurality of antenna elements coupled through vias to the mm-wave radio integrated circuit.

RF transistor amplifiers include an RF transistor amplifier die having a semiconductor layer structure, a coupling element on an upper surface of the semiconductor layer structure, and an interconnect structure on an upper surface of the coupling element so that the RF transistor amplifier die and the interconnect structure are in a stacked arrangement. The coupling element includes a first shielded transmission line structure.

Microelectronic assemblies, and related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first microelectronic component, having a first surface and an opposing second surface including a first direct bonding region at the second surface with first metal contacts and a first dielectric material between adjacent ones of the first metal contacts; a second microelectronic component, having a first surface and an opposing second surface, including a second direct bonding region at the first surface with second metal contacts and a second dielectric material between adjacent ones of the second metal contacts, wherein the second microelectronic component is coupled to the first microelectronic component by the first and second direct bonding regions; and a shield structure in the first direct bonding dielectric material at least partially surrounding the one or more of the first metal contacts.

A semiconductor device having an integrated antenna is provided. The semiconductor device includes a base die having an integrated circuit formed at an active surface and a cap die bonded to the backside surface of the base die. A metal trace is formed over a top surface of the cap die. A cavity is formed under the metal trace. A conductive via is formed through the base die and the cap die interconnecting the metal trace and a conductive trace of the integrated circuit.

A cryptographic device (100) arranged to compute a target block cipher (B.sub.t) on an input message (110), the device comprising a first and second block cipher unit (121, 122) arranged to compute the target block cipher (B.sub.t) on the input message, and a first control unit (130) arranged to take the first block cipher result and the second block cipher result as input, and to produces the first block cipher result only if the block cipher results are equal.

Apparatuses and methods are disclosed herein for the formation of to capacitance through substrate via structures. An example apparatus includes an opening formed in a substrate. Wherein the opening has at least one sidewall, a first dielectric at least formed on the sidewall of the opening, a first conductor at least formed on the first dielectric, a second dielectric at least formed on the first conductor, and a second conductor at least formed on a sidewall of the second dielectric.

A power amplification device includes: a first semiconductor chip including a first main surface and a second main surface; a first field-effect transistor, a first drain finger part, a plurality of first gate finger parts, and a source finger part; a sub-mount substrate including a third main surface and a fourth main surface; and a first filled via provided penetrating from the third main surface to the fourth main surface. In plan view, the first filled via has a rectangular shape. A long side direction of the first filled via is parallel to a long side direction of the plurality of first gate finger parts. In plan view, the first filled via is positioned to overlap part of one first gate finger part included in the plurality of first gate finger parts.

RF transistor amplifiers include an RF transistor amplifier die having a semiconductor layer structure, a coupling element on an upper surface of the semiconductor layer structure, and an interconnect structure on an upper surface of the coupling element so that the RF transistor amplifier die and the interconnect structure are in a stacked arrangement. The coupling element includes a first shielded transmission line structure.

A semiconductor device comprises a substrate having a first surface and a second surface opposite the first surface, at least one connection element arranged on the first surface of the substrate to electrically and mechanically connect the substrate to a printed circuit board, and a radar semiconductor chip arranged on the first surface of the substrate.