An electronic package structure and its manufacturing method are provided. The electronic package structure includes an interposer, a circuit board, a chip, and a circuit structure. The interposer includes an interposer substrate and a coaxial conductive element located in the interposer substrate. The interposer substrate includes a cavity. The coaxial conductive element includes a first conductive structure, a second conductive structure surrounding the first conductive structure, and a first insulation structure. The first insulation structure is disposed between the first and second conductive structures. The circuit board is disposed on a lower surface of the interposer substrate and electrically connected to the coaxial conductive element. The chip is disposed in the cavity and located on the circuit board, so as to be electrically connected to the circuit board. The circuit structure is disposed on an upper surface of the interposer substrate and electrically connected to the coaxial conductive element.

An electronic package structure and manufacturing method thereof. The electronic package structure includes a circuit board, an interposer, a chip, a circuit structure, and a coaxial conductive element. The interposer is disposed on the circuit board. The interposer has a through groove. The chip is disposed in the through groove and located on the circuit board to electrically connect with the circuit board. The circuit structure is disposed on the interposer. The coaxial conductive element penetrates the interposer to electrically connect the circuit structure and the circuit board. The coaxial conductive element includes a first conductive structure, a second conductive structure, and a first insulating structure. The second conductive structure surrounds the first conductive structure. The first insulating structure is disposed between the first conductive structure and the second conductive structure.

Embodiments of a microelectronic package include a package body, radio frequency (RF) circuitry contained in the package body, and a topside input/output (I/O) interface formed on an exterior surface of the package body, and a coaxially-shielded RF interposer. The first coaxially-shielded RF interposer includes a dielectric interposer body, a first signal-carrying via electrically coupled to a topside signal terminal included in the topside I/O interface, and a first coaxial shield structure. The first coaxial shield structure is bonded to the dielectric interposer body, is electrically coupled to a first topside ground terminal further included in the topside I/O interface, and extends at least at least partially around an outer periphery of the signal-carrying via.

Methods and apparatus for providing a cavity defined by conductive walls, a printed circuit board (PCB) within the cavity, and shorting posts extending into the cavity to suppress higher order modes generated by operation of the PCB.

A semiconductor package includes a first semiconductor device, a second semiconductor device vertically positioned above the first semiconductor device, and a ground shielded transmission path. The ground shielded transmission path couples the first semiconductor device to the second semiconductor device. The ground shielded transmission path includes a first signal path extending longitudinally between a first end and a second end. The first signal path includes a conductive material. A first insulating layer is disposed over the signal path longitudinally between the first end and the second end. The first insulating layer includes an electrically insulating material. A ground shielding layer is disposed over the insulating material longitudinally between the first end and the second end of the signal path. The ground shielding layer includes a conductive material coupled to ground. The ground shielding layer drives radiation signals received therein to ground to prevent induced noise in the first signal path.

A transistor according to the disclosure includes a semiconductor substrate, a source pad provided on an upper surface of the semiconductor substrate, a plurality of source electrodes provided on the upper surface of the semiconductor substrate and arranged in an arrangement direction, the plurality of source electrodes each including a first end connected to the source pad and a second end on a side opposite to the source pad, a plurality of drain electrodes arranged alternately with the plurality of source electrodes in the arrangement direction, a gate electrode and a first wire configured to connect the second ends of a plurality of central electrodes provided at a central part of the semiconductor substrate in the arrangement direction among the plurality of source electrodes, and not to connect the second ends of the source electrodes other than the plurality of central electrodes.

A novel and useful a single layer RFIC/MMIC structure including a package and related redistribution layer (RDL) based low loss grounded coplanar transmission line. The structure includes a package molded around an RF circuit die with a single redistribution layer (RDL) fabricated on the surface thereof mounted on an RF printed circuit board (PCB) via a plurality of solder balls. Coplanar transmission lines are fabricated on the RDL to conduct RF output signals from the die to PCB signal solder balls. The signal trace transition to the solder balls are funnel shaped to minimize insertion loss and maximize RF isolation between channels. A conductive ground shield is fabricated on the single RDL and operative to shield the plurality of coplanar transmission lines. The ground shield is electrically connected to a ground plane on the PCB via a plurality of ground solder balls arranged to surround the plurality of coplanar RF transmission lines and signal solder balls, and are operative to couple the ground shield to the ground plane on the PCB and provide an electrical return path for the plurality of coplanar transmission lines. Ground vias on the printed circuit board can be either located under the ground solder balls or between them.

A power amplification device includes: a first semiconductor chip including a first main surface and a second main surface; a first field-effect transistor, a first drain finger part, a plurality of first gate finger parts, and a source finger part; a sub-mount substrate including a third main surface and a fourth main surface; and a first filled via provided penetrating from the third main surface to the fourth main surface. In plan view, the first filled via has a rectangular shape. A long side direction of the first filled via is parallel to a long side direction of the plurality of first gate finger parts. In plan view, the first filled via is positioned to overlap part of one first gate finger part included in the plurality of first gate finger parts.

Methods and apparatus for providing a cavity defined by conductive walls, a printed circuit board (PCB) within the cavity, and shorting posts extending into the cavity to suppress higher order modes generated by operation of the PCB.

The present disclosure relates to an interposer. The interposer includes: a support body formed of a ceramic material, a connection electrode configured to the top surface and bottom surface of the support body, and a shielding member disposed at an outer surface of the support body. At least a part of the support body is disposed along the edge of a substrate, and electrically connects the substrate and a substrate. The interposer is formed of a ceramic material and thus make it possible to implement a fine pattern, to improve dimensional stability by preventing the bending deformation of ceramic green sheets, and to raise the reliability of signal transmission. Therefore, the interposer can contribute to implementing high performance of an electronic device and reducing the size of the electronic device.