An electronic packaging structure including a first circuit structure, a second circuit structure and at least one electronic device is provided. The first circuit structure includes a bottom conductive plate having at least one cavity. The first circuit structure is disposed on the second circuit structure. The first circuit structure and the second circuit structure are electrically connected to each other. The electronic device is disposed on the second circuit structure. The electronic device is disposed corresponding to the cavity of the first circuit structure.

Described examples include an apparatus having a first antenna and a second antenna formed in a first layer on a first surface of a multilayer package substrate, the multilayer package substrate having layers including patterned conductive portions and dielectric portions, the multilayer package substrate having a second surface opposite the first surface. The apparatus also has an isolation wall formed in the multilayer package substrate formed in at least a second and a third layer in the multilayer package substrate and a semiconductor die mounted to the first surface of the multilayer package substrate spaced from and coupled to the first antenna and the second antenna.

A flip chip device includes a substrate, an integrated circuit device, a mold compound, and a via. The substrate has a top side and a bottom side. The integrated circuit device is affixed to the bottom side of the substrate. The mold compound is affixed to the bottom side of the substrate. The via is affixed to the bottom side of the substrate. The via passes through the mold compound and is exposed at a bottom side of the mold compound. The via is coupled to a terminal of the integrated circuit device.

A semiconductor device comprises a substrate having a first surface and a second surface opposite the first surface, at least one connection element arranged on the first surface of the substrate to electrically and mechanically connect the substrate to a printed circuit board, and a radar semiconductor chip arranged on the first surface of the substrate.

An interposer is described. The interposer includes a top layer including an array of passive devices integrated into the top layer. A number of the passive devices may be connected to a pad by a trace disposed above the top layer. The number of the passive devices may be selected to achieve a desired property for the array, such as a desired resistance, inductance, or capacitance. The interposer may thus provide an ability to rapidly tune a die coupled to the pad of the interposer based on the arrangement of the trace.

Integrated circuit (IC) package employing on-package tunable inductor formed in redistribution layer (RDL) for impedance tuner circuit, and related methods. The IC package includes an impedance tuner circuit that includes a tunable inductor that can be tuned to change the frequency response of the impedance tuner circuit. To reduce the circuit area, the tunable inductor is formed in a RDL of a package substrate of the IC package. The IC package also includes a semiconductor die (“die”) that includes other components of the impedance tuner circuit that are coupled to the tunable inductor by the die being coupled to the package substrate. In this manner, by the tunable inductor being formed in a RDL in the package substrate, the signal path lengths between the tunable inductor and other components of the tunable impedance circuit are reduced, thereby reducing inductance path resistance and improving quality (Q) factor of the tunable inductor.

A package comprising an integrated device and a substrate. The integrated device is coupled to the substrate. The substrate includes a core layer, at least one first dielectric layer coupled to a first surface of the core layer, and at least one second dielectric layer coupled to a second surface of the core layer. The substrate includes a match structure located in the core layer. The match structure includes at least one first match interconnect extending vertically and horizontally in the match structure. The match structure also includes at least one second match interconnect extending vertically in the match structure. The at least one first match interconnect and the at least one second match interconnect are configured for skew matching.

The present disclosure provides a package substrate structure and a method for manufacturing the same. The method includes: providing a substrate, forming a first hole with a first radial dimension in the substrate; forming a first metal layer on the sidewall of the first via to form a first via; filing the first via with a dielectric layer; forming a second hole with a second radial dimension in the dielectric layer, wherein the second radial dimension is smaller than the first radial dimension, and the second hole and the first metal layer are separated by the dielectric layer; filling the second hole with the second metal layer to form a second via. The high-speed circuit via design achieved by a sleeve via arrangement of the present disclosure can reduce the influence of the impedance mismatch caused by vias on insertion loss and the return loss in a specific frequency band.

RF transistor amplifiers include an RF transistor amplifier die having a semiconductor layer structure, a coupling element on an upper surface of the semiconductor layer structure, and an interconnect structure on an upper surface of the coupling element so that the RF transistor amplifier die and the interconnect structure are in a stacked arrangement. The coupling element includes a first shielded transmission line structure.

A microelectronics H-frame device includes: a stack of two or more substrates wherein the substrate stack comprises a top substrate and a bottom substrate, wherein bonding of the top substrate to the bottom substrate creates a vertical electrical connection between the top substrate and the bottom substrate, wherein the top surface of the top substrate comprises top substrate top metallization, wherein the bottom surface of the bottom substrate comprises bottom substrate bottom metallization; mid-substrate metallization located between the top substrate and the bottom substrate; a micro-machined top cover bonded to a top side of the substrate stack; and a micro-machined bottom cover bonded to a bottom side of the substrate stack.