Provided are package-on-package (POP)-type semiconductor packages including a lower package having a first size and including a lower package substrate in which a lower semiconductor chip is, an upper redistribution structure on the lower package substrate and the lower semiconductor chip, and alignment marks. The packages may also include an upper package having a second size smaller than the first size and including an upper package substrate and an upper semiconductor chip. The upper package substrate may be mounted on the upper redistribution structure of the lower package and electrically connected to the lower package, and the upper semiconductor chip may be on the upper package substrate. The alignment marks may be used for identifying the upper package, and the alignment marks may be below and near outer boundaries of the upper package on the lower package.

A display device includes a lower substrate, a sub-pixel structure, an optical filter layer, a color filter layer, an upper substrate, and an alignment structure. The lower substrate has a display area and a peripheral area surrounding the display area. The sub-pixel structure is disposed in the display area on the lower substrate. The optical filter layer is disposed on the sub-pixel structure. The color filter layer is disposed on the optical filter layer. The upper substrate is disposed on the color filter layer. The alignment structure is disposed in the peripheral area on a bottom surface of the upper substrate, and contains a material equal to a material forming the optical filter layer and the color filter layer.

A semiconductor device may include a semiconductor die disposed within an encapsulant, the semiconductor die being misaligned with a package edge formed by the encapsulant. A total radial shift of the semiconductor die may account for the misalignment between semiconductor die and the package edge. A build-up interconnect structure may comprise two or more layers formed over the semiconductor die and the encapsulant, the two or more layers comprising at least one redistribution layer (RDL). The total radial shift may be distributed over the two or more layers of the build-up interconnect structure to form a unit specific pattern for each of the two or more layers. An average misalignment of the semiconductor die and the package edge may be greater than the average misalignment of the at least one unit specific pattern with respect to the package edge.

A pattern structure for a display device includes a substrate, a protrusion pattern on the substrate, a first conductive pattern covering an upper surface of the protrusion pattern, an interlayer insulating layer on the first conductive pattern and including a contact hole, and a second conductive pattern on the interlayer insulating layer and connected to the first conductive pattern. The contact hole overlaps the protrusion pattern and the first conductive pattern.

A semiconductor package includes; a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip. The first semiconductor chip includes; a first substrate, a first bonding pad on a first surface of the first substrate, and a first passivation layer on the first surface of the first substrate exposing at least a portion of the first bonding pad. The second semiconductor chip includes; a second substrate, a second insulation layer on a front surface of the second substrate, a second bonding pad on the second insulation layer, a first alignment key pattern on the second insulation layer, and a second passivation layer on the second insulation layer, covering at least a portion of the first alignment key pattern, and exposing at least a portion of the second bonding pad, wherein the first bonding pad and the second bonding pad are directly bonded, and the first passivation layer and the second passivation layer are directly bonded.

An interposer according to an embodiment of the present invention includes a base layer having opposite first and second surfaces, a wiring structure on the first surface of the base layer, an interposer protective layer disposed on the second surface of the base layer and having a pad recess with a lower surface of the interposer protective layer positioned at a first vertical level and a bottom surface of the pad recess positioned at a second vertical level that is higher than the first vertical level, an interposer pad of which a portion fills the pad recess of the interposer protective layer and the remaining portion protrudes from the interposer protective layer, and an interposer through electrode extending through the base layer and the interposer protective layer to the interposer pad, the interposer through electrode electrically connecting the wiring structure to the interposer pad.

An electronic package structure, an electronic substrate, and a method of manufacturing an electronic package structure are provided. The electronic package structure includes a substrate. The substrate includes a bonding region and an alignment structure. The bonding region is located at a side of the substrate and configured to bond with an electronic component. The alignment structure is located at the side of the substrate and out of the bonding region and configured to providing a fiducial mark for position-aligning, wherein the alignment structure comprises a first region and a second region visually distinct from the first region.

A semiconductor device may include a semiconductor die disposed within an encapsulant, the semiconductor die being misaligned with a package edge formed by the encapsulant. A total radial shift of the semiconductor die may account for the misalignment between semiconductor die and the package edge. A build-up interconnect structure may comprise two or more layers formed over the semiconductor die and the encapsulant, the two or more layers comprising at least one redistribution layer (RDL). The total radial shift may be distributed over the two or more layers of the build-up interconnect structure to form a unit specific pattern for each of the two or more layers. An average misalignment of the semiconductor die and the package edge may be greater than the average misalignment of the at least one unit specific pattern with respect to the package edge.

An interposer according to an embodiment of the present invention includes a base layer having opposite first and second surfaces, a wiring structure on the first surface of the base layer, an interposer protective layer disposed on the second surface of the base layer and having a pad recess with a lower surface of the interposer protective layer positioned at a first vertical level and a bottom surface of the pad recess positioned at a second vertical level that is higher than the first vertical level, an interposer pad of which a portion fills the pad recess of the interposer protective layer and the remaining portion protrudes from the interposer protective layer, and an interposer through electrode extending through the base layer and the interposer protective layer to the interposer pad, the interposer through electrode electrically connecting the wiring structure to the interposer pad.

A pattern structure for a display device includes a substrate, a protrusion pattern on the substrate, a first conductive pattern covering an upper surface of the protrusion pattern, an interlayer insulating layer on the first conductive pattern and including a contact hole, and a second conductive pattern on the interlayer insulating layer and connected to the first conductive pattern. The contact hole overlaps the protrusion pattern and the first conductive pattern.