A structure includes a controlled polyimide profile. A method for forming such a structure includes depositing, on a substrate, a photoresist containing polyimide and performing a first anneal at a first temperature. The method further includes exposing the photoresist to a radiation source through a photomask having a pattern associated with a shape of a polyimide opening. The method further includes performing a second anneal at a second temperature and removing a portion of the photoresist to form the polyimide opening. The method further includes performing a third anneal at a third temperature and cleaning the polyimide opening by ashing.

At least one unit transistor is arranged over a substrate. A first wiring as a path of current that flows to each unit transistor is arranged over the at least one unit transistor. An inorganic insulation film is arranged over the first wiring. At least one first opening overlapping a partial region of the first wiring in a plan view is provided in the inorganic insulation film. An organic insulation film is arranged over the inorganic insulation film. A second wiring coupled to the first wiring through the first opening is arranged over the organic insulation film and the inorganic insulation film. In a plan view, a region in which the organic insulation film is not arranged is provided outside a region in which the first wiring is arranged. The second wiring is in contact with the inorganic insulation film outside the region in which the first wiring is arranged.

Provided is a redistribution layer (RDL) structure including a substrate, a pad, a dielectric layer, a self-aligned structure, a conductive layer, and a conductive connector. The pad is disposed on the substrate. The dielectric layer is disposed on the substrate and exposes a portion of the pad. The self-aligned structure is disposed on the dielectric layer. The conductive layer extends from the pad to conformally cover a surface of the self-aligned structure. The conductive connector is disposed on the self-aligned structure. A method of manufacturing the RDL structure is also provided.

A semiconductor device includes a semiconductor body, a stress relieving layer or layer stack disposed over at least part of the semiconductor body, the stress relieving layer or layer stack comprising a plurality of openings which yield a patterned surface topography for the stress relieving layer or layer stack, and a metal layer or layer stack formed on the stress relieving layer or layer stack and occupying the plurality of openings in the stress relieving layer or layer stack. The patterned surface topography of the stress relieving layer or layer stack is transferred to a surface of the metal layer or layer stack facing away from the semiconductor body. The stress relieving layer or layer stack has a different elastic modulus than the metal layer or layer stack over a temperature range.

A package structure includes a first dielectric layer, a first semiconductor device over the first dielectric layer, a first redistribution line in the first dielectric layer, a second dielectric layer over the first semiconductor device, a second semiconductor device over the second dielectric layer, a second redistribution line in the second dielectric layer, a conductive through-via over the first dielectric layer and electrically connected to the first redistribution line, a conductive ball over the conductive through-via and electrically connected to the second redistribution line, and a molding material. The molding material surrounds the first semiconductor device, the conductive through-via, and the conductive ball, wherein a top of the conductive ball is higher than a top of the molding material.

A semiconductor device has a semiconductor die. A first insulating layer is disposed over the semiconductor die. A first via is formed in the first insulating layer over a contact pad of the semiconductor die. A first conductive layer is disposed over the first insulating layer and in the first via. A second insulating layer is disposed over a portion of the first insulating layer and first conductive layer. An island of the second insulating layer is formed over the first conductive layer and within the first via. The first conductive layer adjacent to the island is devoid of the second insulating layer. A second conductive layer is disposed over the first conductive layer, second insulating layer, and island. The second conductive layer has a corrugated structure. A width of the island is greater than a width of the first via.

Semiconductor devices having metallization structures including crack-inhibiting structures, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a metallization structure formed over a semiconductor substrate. The metallization structure can include a bond pad electrically coupled to the semiconductor substrate via one or more layers of conductive material, and an insulating materialsuch as a low- dielectric materialat least partially around the conductive material. The metallization structure can further include a crack-inhibiting structure positioned beneath the bond pad between the bond pad and the semiconductor substrate. The crack-inhibiting structure can include a barrier member extending vertically from the bond pad toward the semiconductor substrate and configured to inhibit crack propagation through the insulating material.

The present disclosure provides a semiconductor package, including a substrate, an active region in the substrate, an interconnecting layer over the active region, a conductive pad over the interconnecting layer, surrounded by a dielectric layer. At least two discrete regions of the conductive pad are free from coverage of the dielectric layer. A method of manufacturing the semiconductor package is also disclosed.

A semiconductor device has a semiconductor die. A first insulating layer is disposed over the semiconductor die. A first via is formed in the first insulating layer over a contact pad of the semiconductor die. A first conductive layer is disposed over the first insulating layer and in the first via. A second insulating layer is disposed over a portion of the first insulating layer and first conductive layer. An island of the second insulating layer is formed over the first conductive layer and within the first via. The first conductive layer adjacent to the island is devoid of the second insulating layer. A second conductive layer is disposed over the first conductive layer, second insulating layer, and island. The second conductive layer has a corrugated structure. A width of the island is greater than a width of the first via.

A method of manufacturing a semiconductor device is provided. The method includes forming a non-conductive layer over an active side of a semiconductor die partially encapsulated with an encapsulant. An opening in the non-conductive layer is formed exposing a portion of a bond pad of the semiconductor die. A laser ablated trench is formed at a surface of the non-conductive layer proximate to a perimeter of the opening. A bottom surface of the laser ablated trench is substantially roughened. An under-bump metallization (UBM) structure is formed over the bond pad and laser ablated trench.