A semiconductor device includes an SiC semiconductor substrate including a diffusion layer, a first electrode provided on the SiC semiconductor substrate, a second electrode provided on the first electrode, and a resin section that is substantially the same size in a plan view as the SiC semiconductor substrate, and that is configured to seal in the second electrode.

A semiconductor device includes an SiC semiconductor substrate including a diffusion layer, a first electrode provided on the SiC semiconductor substrate, a second electrode provided on the first electrode, and a resin section that is substantially the same size in a plan view as the SiC semiconductor substrate, and that is configured to seal in the second electrode.

The semiconductor package has a metal layer, a first dielectric layer formed on a metal layer, and an opening formed through the first dielectric layer to expose a part of the metal layer. The bump structure has an under bump metallurgy (hereinafter UBM), a first buffer layer and a metal bump. The UBM is formed on the first part of the metal layer, a sidewall of the opening and a top surface of the first dielectric layer. The first buffer layer is formed between a part of the UBM corresponding to the top surface of the first dielectric layer and the top surface of the first dielectric layer. The metal bump is formed on the UBM. Therefore, the first buffer layer effectively absorbs a thermal stress to avoid cracks generated in the bump structure after the bonding step.

The semiconductor package has a metal layer, a first dielectric layer formed on a metal layer, and an opening formed through the first dielectric layer to expose a part of the metal layer. The bump structure has an under bump metallurgy (hereinafter UBM), a first buffer layer and a metal bump. The UBM is formed on the first part of the metal layer, a sidewall of the opening and a top surface of the first dielectric layer. The first buffer layer is formed between a part of the UBM corresponding to the top surface of the first dielectric layer and the top surface of the first dielectric layer. The metal bump is formed on the UBM. Therefore, the first buffer layer effectively absorbs a thermal stress to avoid cracks generated in the bump structure after the bonding step.

A semiconductor device structure includes a silicon layer disposed over a first semiconductor die, and a first mask layer disposed over the silicon layer. The semiconductor device structure also includes a second semiconductor die disposed over the first mask layer, and a through silicon via penetrating through the silicon layer and the first mask layer. A bottom surface of the through silicon via is greater than a top surface of the through silicon via, and the top surface of the through silicon via is greater than a cross-section of the through silicon via between and parallel to the top surface and the bottom surface of the through silicon via.

A semiconductor device structure includes a silicon layer disposed over a first semiconductor die, and a first mask layer disposed over the silicon layer. The semiconductor device structure also includes a second semiconductor die disposed over the first mask layer, and a through silicon via penetrating through the silicon layer and the first mask layer. A bottom surface of the through silicon via is greater than a top surface of the through silicon via, and the top surface of the through silicon via is greater than a cross-section of the through silicon via between and parallel to the top surface and the bottom surface of the through silicon via.

A semiconductor device includes a semiconductor substrate having a semiconductor substrate having a main surface including a first portion; a redistribution layer provided over the first portion of the main surface of the semiconductor substrate; an insulating layer covering the first portion of the main surface of the semiconductor substrate and the redistribution layer; and a first polyimide film covering the insulating layer; wherein the polyimide film has a substantially flat upper surface.

A groove is formed between an inner peripheral edge of an opening of a pad electrode and an outer peripheral edge of a bonding region located inside the pad electrode in plan view.

A groove is formed between an inner peripheral edge of an opening of a pad electrode and an outer peripheral edge of a bonding region located inside the pad electrode in plan view.

In some embodiments, the present disclosure relates to a method including forming an interconnect structure over a substrate. A bond pad may be coupled to the interconnect structure, and a polymeric material may be deposited over the bond pad. In some embodiments, the method further includes performing a patterning process to remove a portion of the polymeric material to form an opening in the polymeric material. The opening directly overlies and exposes the bond pad. Further, the method includes a first cleaning process. The polymeric material is cured to form a polymeric protection layer, and a second cleaning process is performed.